On Fri, Nov 12, 2021 at 2:01 AM LIU Zhiwei wrote:
>
> In some cases, we must restore the guest PC to the address of the start of
> the TB, such as when the instruction counter hits zero. So extend pc register
> according to current xlen for these cases.
>
> Signed-off-by: LIU Zhiwei
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/cpu.c| 22 +++---
> target/riscv/cpu.h| 2 ++
> target/riscv/cpu_helper.c | 2 +-
> 3 files changed, 22 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index f812998123..0d2d175fa2 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -319,7 +319,12 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
> {
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = >env;
> -env->pc = value;
> +
> +if (cpu_get_xl(env) == MXL_RV32) {
> +env->pc = (int32_t)value;
> +} else {
> +env->pc = value;
> +}
> }
>
> static void riscv_cpu_synchronize_from_tb(CPUState *cs,
> @@ -327,7 +332,13 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
> {
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = >env;
> -env->pc = tb->pc;
> +RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
> +
> +if (xl == MXL_RV32) {
> +env->pc = (int32_t)tb->pc;
> +} else {
> +env->pc = tb->pc;
> +}
> }
>
> static bool riscv_cpu_has_work(CPUState *cs)
> @@ -348,7 +359,12 @@ static bool riscv_cpu_has_work(CPUState *cs)
> void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
>target_ulong *data)
> {
> -env->pc = data[0];
> +RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
> +if (xl == MXL_RV32) {
> +env->pc = (int32_t)data[0];
> +} else {
> +env->pc = data[0];
> +}
> }
>
> static void riscv_cpu_reset(DeviceState *dev)
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 0760c0af93..8befff0166 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -420,6 +420,8 @@ static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env)
> }
> #endif
>
> +RISCVMXL cpu_get_xl(CPURISCVState *env);
> +
> /*
> * A simplification for VLMAX
> * = (1 << LMUL) * VLEN / (8 * (1 << SEW))
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 4c048cc266..79aba9c880 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -35,7 +35,7 @@ int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch)
> #endif
> }
>
> -static RISCVMXL cpu_get_xl(CPURISCVState *env)
> +RISCVMXL cpu_get_xl(CPURISCVState *env)
> {
> #if defined(TARGET_RISCV32)
> return MXL_RV32;
> --
> 2.25.1
>
>