On Fri, Nov 12, 2021 at 1:54 AM LIU Zhiwei wrote:
>
> Signed-off-by: LIU Zhiwei
> Reviewed-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/gdbstub.c | 71 +++---
> 1 file changed, 52 insertions(+), 19 deletions(-)
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 23429179e2..8d0f9139d7 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -24,11 +24,23 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray
> *mem_buf, int n)
> {
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> +target_ulong tmp;
>
> if (n < 32) {
> -return gdb_get_regl(mem_buf, env->gpr[n]);
> +tmp = env->gpr[n];
> } else if (n == 32) {
> -return gdb_get_regl(mem_buf, env->pc);
> +tmp = env->pc;
> +} else {
> +return 0;
> +}
> +
> +switch (env->misa_mxl_max) {
> +case MXL_RV32:
> +return gdb_get_reg32(mem_buf, tmp);
> +case MXL_RV64:
> +return gdb_get_reg64(mem_buf, tmp);
> +default:
> +g_assert_not_reached();
> }
> return 0;
> }
> @@ -37,18 +49,32 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t
> *mem_buf, int n)
> {
> RISCVCPU *cpu = RISCV_CPU(cs);
> CPURISCVState *env = &cpu->env;
> -
> -if (n == 0) {
> -/* discard writes to x0 */
> -return sizeof(target_ulong);
> -} else if (n < 32) {
> -env->gpr[n] = ldtul_p(mem_buf);
> -return sizeof(target_ulong);
> +int length = 0;
> +target_ulong tmp;
> +
> +switch (env->misa_mxl_max) {
> +case MXL_RV32:
> +tmp = (int32_t)ldl_p(mem_buf);
> +length = 4;
> +break;
> +case MXL_RV64:
> +if (cpu_get_xl(env) < MXL_RV64) {
> +tmp = (int32_t)ldq_p(mem_buf);
> +} else {
> +tmp = ldq_p(mem_buf);
> +}
> +length = 8;
> +break;
> +default:
> +g_assert_not_reached();
> +}
> +if (n > 0 && n < 32) {
> +env->gpr[n] = tmp;
> } else if (n == 32) {
> -env->pc = ldtul_p(mem_buf);
> -return sizeof(target_ulong);
> +env->pc = tmp;
> }
> -return 0;
> +
> +return length;
> }
>
> static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)
> @@ -198,13 +224,20 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState
> *cs)
> gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu,
> 36, "riscv-32bit-fpu.xml", 0);
> }
> -#if defined(TARGET_RISCV32)
> -gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
> riscv_gdb_set_virtual,
> - 1, "riscv-32bit-virtual.xml", 0);
> -#elif defined(TARGET_RISCV64)
> -gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
> riscv_gdb_set_virtual,
> - 1, "riscv-64bit-virtual.xml", 0);
> -#endif
> +switch (env->misa_mxl_max) {
> +case MXL_RV32:
> +gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
> + riscv_gdb_set_virtual,
> + 1, "riscv-32bit-virtual.xml", 0);
> +break;
> +case MXL_RV64:
> +gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
> + riscv_gdb_set_virtual,
> + 1, "riscv-64bit-virtual.xml", 0);
> +break;
> +default:
> +g_assert_not_reached();
> +}
>
> gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,
> riscv_gen_dynamic_csr_xml(cs, cs->gdb_num_regs),
> --
> 2.25.1
>
>
