The following instructions are part of Zbc:
- clmul
- clmulh
- clmulr
Note that these instructions were already defined in the pre-0.93 and
the 0.93 draft-B proposals, but had not been omitted in the earlier
addition of draft-B to QEmu.
Signed-off-by: Philipp Tomsich
---
(no changes since v3)
Changes in v3:
- This adds the Zbc instructions as a spearate commit.
- Uses a helper for clmul/clmulr instead of inlining the calculation of
the result (addressing a comment from Richard Henderson).
target/riscv/bitmanip_helper.c | 27 ++
target/riscv/helper.h | 2 ++
target/riscv/insn32.decode | 5
target/riscv/insn_trans/trans_rvb.c.inc | 37 -
4 files changed, 70 insertions(+), 1 deletion(-)
diff --git a/target/riscv/bitmanip_helper.c b/target/riscv/bitmanip_helper.c
index 5b2f795d03..73be5a81c7 100644
--- a/target/riscv/bitmanip_helper.c
+++ b/target/riscv/bitmanip_helper.c
@@ -3,6 +3,7 @@
*
* Copyright (c) 2020 Kito Cheng, kito.ch...@sifive.com
* Copyright (c) 2020 Frank Chang, frank.ch...@sifive.com
+ * Copyright (c) 2021 Philipp Tomsich, philipp.toms...@vrull.eu
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
@@ -88,3 +89,29 @@ target_ulong HELPER(gorcw)(target_ulong rs1, target_ulong
rs2)
{
return do_gorc(rs1, rs2, 32);
}
+
+target_ulong HELPER(clmul)(target_ulong rs1, target_ulong rs2)
+{
+target_ulong result = 0;
+
+for (int i = 0; i < TARGET_LONG_BITS; i++) {
+if ((rs2 >> i) & 1) {
+result ^= (rs1 << i);
+}
+}
+
+return result;
+}
+
+target_ulong HELPER(clmulr)(target_ulong rs1, target_ulong rs2)
+{
+target_ulong result = 0;
+
+for (int i = 0; i < TARGET_LONG_BITS; i++) {
+if ((rs2 >> i) & 1) {
+result ^= (rs1 >> (TARGET_LONG_BITS - i - 1));
+}
+}
+
+return result;
+}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 415e37bc37..c559c860a7 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -63,6 +63,8 @@ DEF_HELPER_FLAGS_2(grev, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(grevw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(gorc, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_FLAGS_2(gorcw, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(clmul, TCG_CALL_NO_RWG_SE, tl, tl, tl)
+DEF_HELPER_FLAGS_2(clmulr, TCG_CALL_NO_RWG_SE, tl, tl, tl)
/* Special functions */
DEF_HELPER_3(csrrw, tl, env, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 1166e7f648..0471c8 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -713,6 +713,11 @@ roriw 011 .. 101 . 0011011 @sh5
greviw 0110100 .. 101 . 0011011 @sh5
gorciw 0010100 .. 101 . 0011011 @sh5
+# *** RV32 Zbc Standard Extension ***
+clmul 101 .. 001 . 0110011 @r
+clmulh 101 .. 011 . 0110011 @r
+clmulr 101 .. 010 . 0110011 @r
+
# *** RV32 Zbs Standard Extension ***
bclr 0100100 .. 001 . 0110011 @r
bclri 01001. ... 001 . 0010011 @sh
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index 21d713df27..92c31ea1e6 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -1,5 +1,5 @@
/*
- * RISC-V translation routines for the RVB draft Zb[as] Standard Extension.
+ * RISC-V translation routines for the Zb[acs] Standard Extension.
*
* Copyright (c) 2020 Kito Cheng, kito.ch...@sifive.com
* Copyright (c) 2020 Frank Chang, frank.ch...@sifive.com
@@ -24,6 +24,12 @@
}\
} while (0)
+#define REQUIRE_ZBC(ctx) do {\
+if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) { \
+return false;\
+}\
+} while (0)
+
#define REQUIRE_ZBS(ctx) do {\
if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) { \
return false;\
@@ -357,3 +363,32 @@ static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw
*a)
tcg_temp_free(source1);
return true;
}
+
+static bool trans_clmul(DisasContext *ctx, arg_clmul *a)
+{
+REQUIRE_ZBC(ctx);
+return gen_arith(ctx, a, gen_helper_clmul);
+}
+
+static bool trans_clmulh(DisasContext *ctx, arg_clmulr *a)
+{
+REQUIRE_ZBC(ctx);
+
+/* Perform a clmulr ... */
+gen_arith(ctx, a, gen_helper_clmulr);
+
+/* ... then shift the result 1 bit to the right. */
+TCGv dst = tcg_temp_new();
+gen_get_gpr(dst, a->rd);
+tcg_gen_shri_tl(dst, dst, 1);
+gen_set_gpr(a->rd, dst);
+tcg_temp_free(dst);
+
+return true;
+}
+
+static bool trans_clmulr(DisasContext *ctx, arg_clmulh *a)
+{
+
