This includes:
- CSRRD
- CSRWR
- CSRXCHG
Signed-off-by: Xiaojuan Yang
Signed-off-by: Song Gao
---
target/loongarch/csr_helper.c | 87 ++
target/loongarch/disas.c | 101 +++
target/loongarch/helper.h | 8 +
.../insn_trans/trans_privileged.c.inc | 264 ++
target/loongarch/insns.decode | 13 +
target/loongarch/meson.build | 1 +
target/loongarch/translate.c | 11 +-
7 files changed, 484 insertions(+), 1 deletion(-)
create mode 100644 target/loongarch/csr_helper.c
create mode 100644 target/loongarch/insn_trans/trans_privileged.c.inc
diff --git a/target/loongarch/csr_helper.c b/target/loongarch/csr_helper.c
new file mode 100644
index 00..24a9389364
--- /dev/null
+++ b/target/loongarch/csr_helper.c
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * LoongArch emulation helpers for CSRs
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/main-loop.h"
+#include "cpu.h"
+#include "internals.h"
+#include "qemu/host-utils.h"
+#include "exec/helper-proto.h"
+#include "exec/exec-all.h"
+#include "exec/cpu_ldst.h"
+#include "hw/irq.h"
+#include "cpu-csr.h"
+#include "tcg/tcg-ldst.h"
+
+target_ulong helper_csrrd_pgd(CPULoongArchState *env)
+{
+int64_t v;
+
+if (env->CSR_TLBRERA & 0x1) {
+v = env->CSR_TLBRBADV;
+} else {
+v = env->CSR_BADV;
+}
+
+if ((v >> 63) & 0x1) {
+v = env->CSR_PGDH;
+} else {
+v = env->CSR_PGDL;
+}
+
+return v;
+}
+
+target_ulong helper_csrrd_tval(CPULoongArchState *env)
+{
+LoongArchCPU *cpu = env_archcpu(env);
+
+return cpu_loongarch_get_constant_timer_ticks(cpu);
+}
+
+target_ulong helper_csrwr_estat(CPULoongArchState *env, target_ulong val)
+{
+int64_t old_v = env->CSR_ESTAT;
+
+/* Only IS[1:0] can be written */
+env->CSR_ESTAT = deposit64(env->CSR_ESTAT, 0, 2, val);
+
+return old_v;
+}
+
+target_ulong helper_csrwr_asid(CPULoongArchState *env, target_ulong val)
+{
+int64_t old_v = env->CSR_ASID;
+
+/* Only ASID filed of CSR_ASID can be written */
+env->CSR_ASID = deposit64(env->CSR_ASID, 0, 10, val);
+if (old_v != env->CSR_ASID) {
+tlb_flush(env_cpu(env));
+}
+return old_v;
+}
+
+target_ulong helper_csrwr_tcfg(CPULoongArchState *env, target_ulong val)
+{
+LoongArchCPU *cpu = env_archcpu(env);
+int64_t old_v = env->CSR_TCFG;
+
+cpu_loongarch_store_constant_timer_config(cpu, val);
+
+return old_v;
+}
+
+target_ulong helper_csrwr_ticlr(CPULoongArchState *env, target_ulong val)
+{
+LoongArchCPU *cpu = env_archcpu(env);
+int64_t old_v = 0;
+
+if (val & 0x1) {
+loongarch_cpu_set_irq(cpu, IRQ_TIMER, 0);
+}
+return old_v;
+}
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c
index 9454ebb8e9..11a704ff7c 100644
--- a/target/loongarch/disas.c
+++ b/target/loongarch/disas.c
@@ -8,6 +8,7 @@
#include "qemu/osdep.h"
#include "disas/dis-asm.h"
#include "qemu/bitops.h"
+#include "cpu-csr.h"
typedef struct {
disassemble_info *info;
@@ -25,6 +26,90 @@ static inline int shl_2(DisasContext *ctx, int x)
return x << 2;
}
+#define CSR_NAME(REG) \
+[LOONGARCH_CSR_##REG] = (#REG)
+
+static const char * const csr_names[] = {
+CSR_NAME(CRMD),
+CSR_NAME(PRMD),
+CSR_NAME(EUEN),
+CSR_NAME(MISC),
+CSR_NAME(ECFG),
+CSR_NAME(ESTAT),
+CSR_NAME(ERA),
+CSR_NAME(BADV),
+CSR_NAME(BADI),
+CSR_NAME(EENTRY),
+CSR_NAME(TLBIDX),
+CSR_NAME(TLBEHI),
+CSR_NAME(TLBELO0),
+CSR_NAME(TLBELO1),
+CSR_NAME(ASID),
+CSR_NAME(PGDL),
+CSR_NAME(PGDH),
+CSR_NAME(PGD),
+CSR_NAME(PWCL),
+CSR_NAME(PWCH),
+CSR_NAME(STLBPS),
+CSR_NAME(RVACFG),
+CSR_NAME(CPUID),
+CSR_NAME(PRCFG1),
+CSR_NAME(PRCFG2),
+CSR_NAME(PRCFG3),
+CSR_NAME(SAVE(0)),
+CSR_NAME(SAVE(1)),
+CSR_NAME(SAVE(2)),
+CSR_NAME(SAVE(3)),
+CSR_NAME(SAVE(4)),
+CSR_NAME(SAVE(5)),
+CSR_NAME(SAVE(6)),
+CSR_NAME(SAVE(7)),
+CSR_NAME(SAVE(8)),
+CSR_NAME(SAVE(9)),
+CSR_NAME(SAVE(10)),
+CSR_NAME(SAVE(11)),
+CSR_NAME(SAVE(12)),
+CSR_NAME(SAVE(13)),
+CSR_NAME(SAVE(14)),
+CSR_NAME(SAVE(15)),
+CSR_NAME(TID),
+CSR_NAME(TCFG),
+CSR_NAME(TVAL),
+CSR_NAME(CNTC),
+CSR_NAME(TICLR),
+CSR_NAME(LLBCTL),
+CSR_NAME(IMPCTL1),
+CSR_NAME(IMPCTL2),
+CSR_NAME(TLBRENTRY),
+CSR_NAME(TLBRBADV),
+CSR_NAME(TLBRERA),
+CSR_NAME(TLBRSAVE),
+CSR_NAME(TLBRELO0),
+CSR_NAME(TLBRELO1),
+CSR_NAME(TLBREHI),
+CSR_NAME(TLBRPRMD),
+CSR_NAME(MERRCTL),
+CSR_NAME(MERRINFO1),
+CSR_NAME(MERRINFO2),
+CSR_NAME(MERRENTRY),
+CSR_NAME(MERRERA),
+CSR_NAME(MERRSAVE),
+CSR_NAME(CTAG),
+CSR_NAME(DMW(0)),
+CSR_NAME(DMW(1)),
+CSR_NAME(DMW(2)),
+
