On Wed, 31 Mar 2021 12:37:08 -0400
Chris Browy wrote:
> From: hchkuo
>
> Signed-off-by: hchkuo
Code must build after each patch, so this needs to go first in the series,
not last. git rebase -i HEAD~3 and reorder the patches should be an easy
way to do it.
+ add a note to say standard-headers at least should come via scripts
(break that one out to a separate patch to make life easier)
Jonathan
> ---
> include/hw/pci/pci_ids.h | 2 ++
> include/hw/pci/pcie_regs.h| 3 +++
> include/standard-headers/linux/pci_regs.h | 3 ++-
> 3 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h
> index 95f92d9..471c915 100644
> --- a/include/hw/pci/pci_ids.h
> +++ b/include/hw/pci/pci_ids.h
> @@ -157,6 +157,8 @@
>
> /* Vendors and devices. Sort key: vendor first, device next. */
>
> +#define PCI_VENDOR_ID_PCI_SIG0x0001
> +
> #define PCI_VENDOR_ID_LSI_LOGIC 0x1000
> #define PCI_DEVICE_ID_LSI_53C810 0x0001
> #define PCI_DEVICE_ID_LSI_53C895A0x0012
> diff --git a/include/hw/pci/pcie_regs.h b/include/hw/pci/pcie_regs.h
> index 1db86b0..5ec7014 100644
> --- a/include/hw/pci/pcie_regs.h
> +++ b/include/hw/pci/pcie_regs.h
> @@ -179,4 +179,7 @@ typedef enum PCIExpLinkWidth {
> #define PCI_ACS_VER 0x1
> #define PCI_ACS_SIZEOF 8
>
> +/* DOE Capability Register Fields */
> +#define PCI_DOE_SIZEOF 24
> +
> #endif /* QEMU_PCIE_REGS_H */
> diff --git a/include/standard-headers/linux/pci_regs.h
> b/include/standard-headers/linux/pci_regs.h
> index e709ae8..2a8df63 100644
> --- a/include/standard-headers/linux/pci_regs.h
> +++ b/include/standard-headers/linux/pci_regs.h
> @@ -730,7 +730,8 @@
> #define PCI_EXT_CAP_ID_DVSEC 0x23/* Designated Vendor-Specific */
> #define PCI_EXT_CAP_ID_DLF 0x25/* Data Link Feature */
> #define PCI_EXT_CAP_ID_PL_16GT 0x26/* Physical Layer 16.0 GT/s */
> -#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT
> +#define PCI_EXT_CAP_ID_DOE 0x2E/* Data Object Exchange */
> +#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_DOE
>
> #define PCI_EXT_CAP_DSN_SIZEOF 12
> #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
