[PATCH v5 04/14] target/riscv: Remove the W-form instructions from Zbs
Zbs 1.0.0 (just as the 0.93 draft-B before) does no provide for W-form
instructions for Zbs (single-bit instructions). Remove them.
Note that these instructions had already been removed for the 0.93
version of the draft-B extenstion and have not been present in the
binutils patches circulating in January 2021.
Signed-off-by: Philipp Tomsich
Reviewed-by: Richard Henderson
---
(no changes since v3)
Changes in v3:
- Remove the W-form instructions from Zbs in a separate commit.
target/riscv/insn32.decode | 7
target/riscv/insn_trans/trans_rvb.c.inc | 49 -
2 files changed, 56 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 68b163b72d..9abdbcb799 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -716,10 +716,6 @@ cpopw 011 00010 . 001 . 0011011 @r2
packw 100 .. 100 . 0111011 @r
packuw 0100100 .. 100 . 0111011 @r
-bsetw 0010100 .. 001 . 0111011 @r
-bclrw 0100100 .. 001 . 0111011 @r
-binvw 0110100 .. 001 . 0111011 @r
-bextw 0100100 .. 101 . 0111011 @r
slow 001 .. 001 . 0111011 @r
srow 001 .. 101 . 0111011 @r
rorw 011 .. 101 . 0111011 @r
@@ -727,9 +723,6 @@ rolw 011 .. 001 . 0111011 @r
grevw 0110100 .. 101 . 0111011 @r
gorcw 0010100 .. 101 . 0111011 @r
-bsetiw 0010100 .. 001 . 0011011 @sh5
-bclriw 0100100 .. 001 . 0011011 @sh5
-binviw 0110100 .. 001 . 0011011 @sh5
sloiw 001 .. 001 . 0011011 @sh5
sroiw 001 .. 101 . 0011011 @sh5
roriw 011 .. 101 . 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index dcc7b6893d..975492d45c 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -279,55 +279,6 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
return gen_arith(ctx, a, gen_packuw);
}
-static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
-{
-REQUIRE_64BIT(ctx);
-REQUIRE_EXT(ctx, RVB);
-return gen_shiftw(ctx, a, gen_bset);
-}
-
-static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a)
-{
-REQUIRE_64BIT(ctx);
-REQUIRE_EXT(ctx, RVB);
-return gen_shiftiw(ctx, a, gen_bset);
-}
-
-static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a)
-{
-REQUIRE_64BIT(ctx);
-REQUIRE_EXT(ctx, RVB);
-return gen_shiftw(ctx, a, gen_bclr);
-}
-
-static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a)
-{
-REQUIRE_64BIT(ctx);
-REQUIRE_EXT(ctx, RVB);
-return gen_shiftiw(ctx, a, gen_bclr);
-}
-
-static bool trans_binvw(DisasContext *ctx, arg_binvw *a)
-{
-REQUIRE_64BIT(ctx);
-REQUIRE_EXT(ctx, RVB);
-return gen_shiftw(ctx, a, gen_binv);
-}
-
-static bool trans_binviw(DisasContext *ctx, arg_binviw *a)
-{
-REQUIRE_64BIT(ctx);
-REQUIRE_EXT(ctx, RVB);
-return gen_shiftiw(ctx, a, gen_binv);
-}
-
-static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
-{
-REQUIRE_64BIT(ctx);
-REQUIRE_EXT(ctx, RVB);
-return gen_shiftw(ctx, a, gen_bext);
-}
-
static bool trans_slow(DisasContext *ctx, arg_slow *a)
{
REQUIRE_64BIT(ctx);
--
2.25.1
[PATCH v5 04/14] target/riscv: Remove the W-form instructions from Zbs
Zbs 1.0.0 (just as the 0.93 draft-B before) does no provide for W-form
instructions for Zbs (single-bit instructions). Remove them.
Note that these instructions had already been removed for the 0.93
version of the draft-B extenstion and have not been present in the
binutils patches circulating in January 2021.
Signed-off-by: Philipp Tomsich
Reviewed-by: Richard Henderson
---
(no changes since v3)
Changes in v3:
- Remove the W-form instructions from Zbs in a separate commit.
target/riscv/insn32.decode | 7
target/riscv/insn_trans/trans_rvb.c.inc | 49 -
2 files changed, 56 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 68b163b72d..9abdbcb799 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -716,10 +716,6 @@ cpopw 011 00010 . 001 . 0011011 @r2
packw 100 .. 100 . 0111011 @r
packuw 0100100 .. 100 . 0111011 @r
-bsetw 0010100 .. 001 . 0111011 @r
-bclrw 0100100 .. 001 . 0111011 @r
-binvw 0110100 .. 001 . 0111011 @r
-bextw 0100100 .. 101 . 0111011 @r
slow 001 .. 001 . 0111011 @r
srow 001 .. 101 . 0111011 @r
rorw 011 .. 101 . 0111011 @r
@@ -727,9 +723,6 @@ rolw 011 .. 001 . 0111011 @r
grevw 0110100 .. 101 . 0111011 @r
gorcw 0010100 .. 101 . 0111011 @r
-bsetiw 0010100 .. 001 . 0011011 @sh5
-bclriw 0100100 .. 001 . 0011011 @sh5
-binviw 0110100 .. 001 . 0011011 @sh5
sloiw 001 .. 001 . 0011011 @sh5
sroiw 001 .. 101 . 0011011 @sh5
roriw 011 .. 101 . 0011011 @sh5
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index dcc7b6893d..975492d45c 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -279,55 +279,6 @@ static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
return gen_arith(ctx, a, gen_packuw);
}
-static bool trans_bsetw(DisasContext *ctx, arg_bsetw *a)
-{
-REQUIRE_64BIT(ctx);
-REQUIRE_EXT(ctx, RVB);
-return gen_shiftw(ctx, a, gen_bset);
-}
-
-static bool trans_bsetiw(DisasContext *ctx, arg_bsetiw *a)
-{
-REQUIRE_64BIT(ctx);
-REQUIRE_EXT(ctx, RVB);
-return gen_shiftiw(ctx, a, gen_bset);
-}
-
-static bool trans_bclrw(DisasContext *ctx, arg_bclrw *a)
-{
-REQUIRE_64BIT(ctx);
-REQUIRE_EXT(ctx, RVB);
-return gen_shiftw(ctx, a, gen_bclr);
-}
-
-static bool trans_bclriw(DisasContext *ctx, arg_bclriw *a)
-{
-REQUIRE_64BIT(ctx);
-REQUIRE_EXT(ctx, RVB);
-return gen_shiftiw(ctx, a, gen_bclr);
-}
-
-static bool trans_binvw(DisasContext *ctx, arg_binvw *a)
-{
-REQUIRE_64BIT(ctx);
-REQUIRE_EXT(ctx, RVB);
-return gen_shiftw(ctx, a, gen_binv);
-}
-
-static bool trans_binviw(DisasContext *ctx, arg_binviw *a)
-{
-REQUIRE_64BIT(ctx);
-REQUIRE_EXT(ctx, RVB);
-return gen_shiftiw(ctx, a, gen_binv);
-}
-
-static bool trans_bextw(DisasContext *ctx, arg_bextw *a)
-{
-REQUIRE_64BIT(ctx);
-REQUIRE_EXT(ctx, RVB);
-return gen_shiftw(ctx, a, gen_bext);
-}
-
static bool trans_slow(DisasContext *ctx, arg_slow *a)
{
REQUIRE_64BIT(ctx);
--
2.25.1
