On Tue, Mar 23, 2021 at 12:43:35PM -0600, Richard Henderson wrote:
> Perform the test against FSCR_SCV at runtime, in the helper.
>
> This means we can remove the incorrect set against SCV in
> ppc_tr_init_disas_context and do not need to add an HFLAGS bit.
>
> Signed-off-by: Richard Henderson
Applied to ppc-for-6.0.
> ---
> target/ppc/helper.h | 1 +
> target/ppc/excp_helper.c | 9 +
> target/ppc/translate.c | 20 +++-
> 3 files changed, 17 insertions(+), 13 deletions(-)
>
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index 6a4dccf70c..513066d54d 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -13,6 +13,7 @@ DEF_HELPER_1(rfci, void, env)
> DEF_HELPER_1(rfdi, void, env)
> DEF_HELPER_1(rfmci, void, env)
> #if defined(TARGET_PPC64)
> +DEF_HELPER_2(scv, noreturn, env, i32)
> DEF_HELPER_2(pminsn, void, env, i32)
> DEF_HELPER_1(rfid, void, env)
> DEF_HELPER_1(rfscv, void, env)
> diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
> index 85de7e6c90..5c95e0c103 100644
> --- a/target/ppc/excp_helper.c
> +++ b/target/ppc/excp_helper.c
> @@ -1130,6 +1130,15 @@ void helper_store_msr(CPUPPCState *env, target_ulong
> val)
> }
>
> #if defined(TARGET_PPC64)
> +void helper_scv(CPUPPCState *env, uint32_t lev)
> +{
> +if (env->spr[SPR_FSCR] & (1ull << FSCR_SCV)) {
> +raise_exception_err(env, POWERPC_EXCP_SYSCALL_VECTORED, lev);
> +} else {
> +raise_exception_err(env, POWERPC_EXCP_FU, FSCR_IC_SCV);
> +}
> +}
> +
> void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_t insn)
> {
> CPUState *cs;
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 7912495f28..d48c554290 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -173,7 +173,6 @@ struct DisasContext {
> bool vsx_enabled;
> bool spe_enabled;
> bool tm_enabled;
> -bool scv_enabled;
> bool gtse;
> ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
> int singlestep_enabled;
> @@ -4081,15 +4080,16 @@ static void gen_sc(DisasContext *ctx)
> #if !defined(CONFIG_USER_ONLY)
> static void gen_scv(DisasContext *ctx)
> {
> -uint32_t lev;
> +uint32_t lev = (ctx->opcode >> 5) & 0x7F;
>
> -if (unlikely(!ctx->scv_enabled)) {
> -gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_SCV);
> -return;
> +/* Set the PC back to the faulting instruction. */
> +if (ctx->exception == POWERPC_EXCP_NONE) {
> +gen_update_nip(ctx, ctx->base.pc_next - 4);
> }
> +gen_helper_scv(cpu_env, tcg_constant_i32(lev));
>
> -lev = (ctx->opcode >> 5) & 0x7F;
> -gen_exception_err(ctx, POWERPC_SYSCALL_VECTORED, lev);
> +/* This need not be exact, just not POWERPC_EXCP_NONE */
> +ctx->exception = POWERPC_SYSCALL_VECTORED;
> }
> #endif
> #endif
> @@ -7907,12 +7907,6 @@ static void ppc_tr_init_disas_context(DisasContextBase
> *dcbase, CPUState *cs)
> ctx->spe_enabled = (hflags >> HFLAGS_SPE) & 1;
> ctx->altivec_enabled = (hflags >> HFLAGS_VR) & 1;
> ctx->vsx_enabled = (hflags >> HFLAGS_VSX) & 1;
> -if ((env->flags & POWERPC_FLAG_SCV)
> -&& (env->spr[SPR_FSCR] & (1ull << FSCR_SCV))) {
> -ctx->scv_enabled = true;
> -} else {
> -ctx->scv_enabled = false;
> -}
> ctx->tm_enabled = (hflags >> HFLAGS_TM) & 1;
> ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE);
>
--
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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