subject:"\[PATCH v5 06\/18\] target\/riscv\: array for the 64 upper bits of 128\-bit registers"

Re: [PATCH v5 06/18] target/riscv: array for the 64 upper bits of 128-bit registers

2021-11-23 Thread Alistair Francis

On Tue, Nov 23, 2021 at 8:58 PM Frédéric Pétrot
 wrote:
>
> On 23/11/2021 07:09, Alistair Francis wrote:
> > On Sat, Nov 13, 2021 at 1:07 AM Frédéric Pétrot
> >  wrote:
> >> +static bool rv128_needed(void *opaque)
> >> +{
> >> +RISCVCPU *cpu = opaque;
> >> +CPURISCVState *env = >env;
> >> +
> >> +return env->misa_mxl_max == MXL_RV128;
> >> +}
> >
> > I think it would just be better to use riscv_cpu_mxl() directly
> > instead of adding a new function here.
>
>Ok, thanks.
>I was doing that because as Zhiwei is progressing on the dynamic handling
>of xlen, in the end the "current" mxl could be different from mxl_max, and
>some state to be saved might live in the registers upper 64-bit.
>But you are quite right that we are not there yet, so I'll do that.

Ah! You are right.

Ignore me, what you have originally looks good!

Reviewed-by: Alistair Francis 

Alistair

>
>Frédéric
> --
> +---+
> | Frédéric Pétrot, Pr. Grenoble INP-Ensimag/TIMA,   Ensimag deputy director |
> | Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70  Ad augusta  per angusta |
> | http://tima.univ-grenoble-alpes.fr frederic.pet...@univ-grenoble-alpes.fr |
> +---+

Re: [PATCH v5 06/18] target/riscv: array for the 64 upper bits of 128-bit registers

2021-11-23 Thread Frédéric Pétrot


On 23/11/2021 07:09, Alistair Francis wrote:

On Sat, Nov 13, 2021 at 1:07 AM Frédéric Pétrot
 wrote:

+static bool rv128_needed(void *opaque)
+{
+RISCVCPU *cpu = opaque;
+CPURISCVState *env = >env;
+
+return env->misa_mxl_max == MXL_RV128;
+}


I think it would just be better to use riscv_cpu_mxl() directly
instead of adding a new function here.


  Ok, thanks.
  I was doing that because as Zhiwei is progressing on the dynamic handling
  of xlen, in the end the "current" mxl could be different from mxl_max, and
  some state to be saved might live in the registers upper 64-bit.
  But you are quite right that we are not there yet, so I'll do that.

  Frédéric
--
+---+
| Frédéric Pétrot, Pr. Grenoble INP-Ensimag/TIMA,   Ensimag deputy director |
| Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70  Ad augusta  per angusta |
| http://tima.univ-grenoble-alpes.fr frederic.pet...@univ-grenoble-alpes.fr |
+---+

Re: [PATCH v5 06/18] target/riscv: array for the 64 upper bits of 128-bit registers

2021-11-22 Thread Alistair Francis

On Sat, Nov 13, 2021 at 1:07 AM Frédéric Pétrot
 wrote:
>
> The upper 64-bit of the 128-bit registers have now a place inside
> the cpu state structure, and are created as globals for future use.
>
> Signed-off-by: Frédéric Pétrot 
> Co-authored-by: Fabien Portas 
> ---
>  target/riscv/cpu.h   |  2 ++
>  target/riscv/cpu.c   |  9 +
>  target/riscv/machine.c   | 20 
>  target/riscv/translate.c |  5 -
>  4 files changed, 35 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 0760c0af93..53a295efb7 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -110,6 +110,7 @@ FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
>
>  struct CPURISCVState {
>  target_ulong gpr[32];
> +target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
>  uint64_t fpr[32]; /* assume both F and D extensions */
>
>  /* vector coprocessor state. */
> @@ -339,6 +340,7 @@ static inline bool riscv_feature(CPURISCVState *env, int 
> feature)
>  #include "cpu_user.h"
>
>  extern const char * const riscv_int_regnames[];
> +extern const char * const riscv_int_regnamesh[];
>  extern const char * const riscv_fpr_regnames[];
>
>  const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index f812998123..364140f5ff 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -42,6 +42,15 @@ const char * const riscv_int_regnames[] = {
>"x28/t3",  "x29/t4", "x30/t5", "x31/t6"
>  };
>
> +const char * const riscv_int_regnamesh[] = {
> +  "x0h/zeroh", "x1h/rah",  "x2h/sph",   "x3h/gph",   "x4h/tph",  "x5h/t0h",
> +  "x6h/t1h",   "x7h/t2h",  "x8h/s0h",   "x9h/s1h",   "x10h/a0h", "x11h/a1h",
> +  "x12h/a2h",  "x13h/a3h", "x14h/a4h",  "x15h/a5h",  "x16h/a6h", "x17h/a7h",
> +  "x18h/s2h",  "x19h/s3h", "x20h/s4h",  "x21h/s5h",  "x22h/s6h", "x23h/s7h",
> +  "x24h/s8h",  "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h",
> +  "x30h/t5h",  "x31h/t6h"
> +};
> +
>  const char * const riscv_fpr_regnames[] = {
>"f0/ft0",   "f1/ft1",  "f2/ft2",   "f3/ft3",   "f4/ft4",  "f5/ft5",
>"f6/ft6",   "f7/ft7",  "f8/fs0",   "f9/fs1",   "f10/fa0", "f11/fa1",
> diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> index 7b4c739564..7e2d02457e 100644
> --- a/target/riscv/machine.c
> +++ b/target/riscv/machine.c
> @@ -92,6 +92,14 @@ static bool pointermasking_needed(void *opaque)
>  return riscv_has_ext(env, RVJ);
>  }
>
> +static bool rv128_needed(void *opaque)
> +{
> +RISCVCPU *cpu = opaque;
> +CPURISCVState *env = >env;
> +
> +return env->misa_mxl_max == MXL_RV128;
> +}

I think it would just be better to use riscv_cpu_mxl() directly
instead of adding a new function here.

Alistair

> +
>  static const VMStateDescription vmstate_vector = {
>  .name = "cpu/vector",
>  .version_id = 1,
> @@ -164,6 +172,17 @@ static const VMStateDescription vmstate_hyper = {
>  }
>  };
>
> +static const VMStateDescription vmstate_rv128 = {
> +.name = "cpu/rv128",
> +.version_id = 1,
> +.minimum_version_id = 1,
> +.needed = rv128_needed,
> +.fields = (VMStateField[]) {
> +VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32),
> +VMSTATE_END_OF_LIST()
> +}
> +};
> +
>  const VMStateDescription vmstate_riscv_cpu = {
>  .name = "cpu",
>  .version_id = 3,
> @@ -218,6 +237,7 @@ const VMStateDescription vmstate_riscv_cpu = {
>  _hyper,
>  _vector,
>  _pointermasking,
> +_rv128,
>  NULL
>  }
>  };
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index b4278a6a92..00a2cfa917 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -32,7 +32,7 @@
>  #include "instmap.h"
>
>  /* global register indices */
> -static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
> +static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl;
>  static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
>  static TCGv load_res;
>  static TCGv load_val;
> @@ -777,10 +777,13 @@ void riscv_translate_init(void)
>   * unless you specifically block reads/writes to reg 0.
>   */
>  cpu_gpr[0] = NULL;
> +cpu_gprh[0] = NULL;
>
>  for (i = 1; i < 32; i++) {
>  cpu_gpr[i] = tcg_global_mem_new(cpu_env,
>  offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
> +cpu_gprh[i] = tcg_global_mem_new(cpu_env,
> +offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]);
>  }
>
>  for (i = 0; i < 32; i++) {
> --
> 2.33.1
>
>

[PATCH v5 06/18] target/riscv: array for the 64 upper bits of 128-bit registers

2021-11-12 Thread Frédéric Pétrot

The upper 64-bit of the 128-bit registers have now a place inside
the cpu state structure, and are created as globals for future use.

Signed-off-by: Frédéric Pétrot 
Co-authored-by: Fabien Portas 
---
 target/riscv/cpu.h   |  2 ++
 target/riscv/cpu.c   |  9 +
 target/riscv/machine.c   | 20 
 target/riscv/translate.c |  5 -
 4 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0760c0af93..53a295efb7 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -110,6 +110,7 @@ FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
 
 struct CPURISCVState {
 target_ulong gpr[32];
+target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */
 uint64_t fpr[32]; /* assume both F and D extensions */
 
 /* vector coprocessor state. */
@@ -339,6 +340,7 @@ static inline bool riscv_feature(CPURISCVState *env, int 
feature)
 #include "cpu_user.h"
 
 extern const char * const riscv_int_regnames[];
+extern const char * const riscv_int_regnamesh[];
 extern const char * const riscv_fpr_regnames[];
 
 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f812998123..364140f5ff 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -42,6 +42,15 @@ const char * const riscv_int_regnames[] = {
   "x28/t3",  "x29/t4", "x30/t5", "x31/t6"
 };
 
+const char * const riscv_int_regnamesh[] = {
+  "x0h/zeroh", "x1h/rah",  "x2h/sph",   "x3h/gph",   "x4h/tph",  "x5h/t0h",
+  "x6h/t1h",   "x7h/t2h",  "x8h/s0h",   "x9h/s1h",   "x10h/a0h", "x11h/a1h",
+  "x12h/a2h",  "x13h/a3h", "x14h/a4h",  "x15h/a5h",  "x16h/a6h", "x17h/a7h",
+  "x18h/s2h",  "x19h/s3h", "x20h/s4h",  "x21h/s5h",  "x22h/s6h", "x23h/s7h",
+  "x24h/s8h",  "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h",
+  "x30h/t5h",  "x31h/t6h"
+};
+
 const char * const riscv_fpr_regnames[] = {
   "f0/ft0",   "f1/ft1",  "f2/ft2",   "f3/ft3",   "f4/ft4",  "f5/ft5",
   "f6/ft6",   "f7/ft7",  "f8/fs0",   "f9/fs1",   "f10/fa0", "f11/fa1",
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 7b4c739564..7e2d02457e 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -92,6 +92,14 @@ static bool pointermasking_needed(void *opaque)
 return riscv_has_ext(env, RVJ);
 }
 
+static bool rv128_needed(void *opaque)
+{
+RISCVCPU *cpu = opaque;
+CPURISCVState *env = >env;
+
+return env->misa_mxl_max == MXL_RV128;
+}
+
 static const VMStateDescription vmstate_vector = {
 .name = "cpu/vector",
 .version_id = 1,
@@ -164,6 +172,17 @@ static const VMStateDescription vmstate_hyper = {
 }
 };
 
+static const VMStateDescription vmstate_rv128 = {
+.name = "cpu/rv128",
+.version_id = 1,
+.minimum_version_id = 1,
+.needed = rv128_needed,
+.fields = (VMStateField[]) {
+VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32),
+VMSTATE_END_OF_LIST()
+}
+};
+
 const VMStateDescription vmstate_riscv_cpu = {
 .name = "cpu",
 .version_id = 3,
@@ -218,6 +237,7 @@ const VMStateDescription vmstate_riscv_cpu = {
 _hyper,
 _vector,
 _pointermasking,
+_rv128,
 NULL
 }
 };
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index b4278a6a92..00a2cfa917 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -32,7 +32,7 @@
 #include "instmap.h"
 
 /* global register indices */
-static TCGv cpu_gpr[32], cpu_pc, cpu_vl;
+static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl;
 static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */
 static TCGv load_res;
 static TCGv load_val;
@@ -777,10 +777,13 @@ void riscv_translate_init(void)
  * unless you specifically block reads/writes to reg 0.
  */
 cpu_gpr[0] = NULL;
+cpu_gprh[0] = NULL;
 
 for (i = 1; i < 32; i++) {
 cpu_gpr[i] = tcg_global_mem_new(cpu_env,
 offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
+cpu_gprh[i] = tcg_global_mem_new(cpu_env,
+offsetof(CPURISCVState, gprh[i]), riscv_int_regnamesh[i]);
 }
 
 for (i = 0; i < 32; i++) {
-- 
2.33.1

Re: [PATCH v5 06/18] target/riscv: array for the 64 upper bits of 128-bit registers

Re: [PATCH v5 06/18] target/riscv: array for the 64 upper bits of 128-bit registers

Re: [PATCH v5 06/18] target/riscv: array for the 64 upper bits of 128-bit registers

[PATCH v5 06/18] target/riscv: array for the 64 upper bits of 128-bit registers

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