Re: [PATCH v5 20/24] target/riscv: Use gen_shift_imm_fn for slli_uw

[Alistair Francis]

On Tue, Aug 24, 2021 at 6:09 AM Richard Henderson
 wrote:
>
> Always use tcg_gen_deposit_z_tl; the special case for
> shamt >= 32 is handled there.
>
> Signed-off-by: Richard Henderson 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/insn_trans/trans_rvb.c.inc | 19 ++-
>  1 file changed, 6 insertions(+), 13 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc 
> b/target/riscv/insn_trans/trans_rvb.c.inc
> index b97c3ca5da..b72e76255c 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -635,21 +635,14 @@ static bool trans_add_uw(DisasContext *ctx, arg_add_uw 
> *a)
>  return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
>  }
>
> +static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
> +{
> +tcg_gen_deposit_z_tl(dest, src, shamt, MIN(32, TARGET_LONG_BITS - 
> shamt));
> +}
> +
>  static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
>  {
>  REQUIRE_64BIT(ctx);
>  REQUIRE_EXT(ctx, RVB);
> -
> -TCGv source1 = tcg_temp_new();
> -gen_get_gpr(ctx, source1, a->rs1);
> -
> -if (a->shamt < 32) {
> -tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32);
> -} else {
> -tcg_gen_shli_tl(source1, source1, a->shamt);
> -}
> -
> -gen_set_gpr(ctx, a->rd, source1);
> -tcg_temp_free(source1);
> -return true;
> +return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
>  }
> --
> 2.25.1
>
>

[PATCH v5 20/24] target/riscv: Use gen_shift_imm_fn for slli_uw

[Richard Henderson]

Always use tcg_gen_deposit_z_tl; the special case for
shamt >= 32 is handled there.

Signed-off-by: Richard Henderson 
---
 target/riscv/insn_trans/trans_rvb.c.inc | 19 ++-
 1 file changed, 6 insertions(+), 13 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvb.c.inc 
b/target/riscv/insn_trans/trans_rvb.c.inc
index b97c3ca5da..b72e76255c 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -635,21 +635,14 @@ static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
 return gen_arith(ctx, a, EXT_NONE, gen_add_uw);
 }
 
+static void gen_slli_uw(TCGv dest, TCGv src, target_long shamt)
+{
+tcg_gen_deposit_z_tl(dest, src, shamt, MIN(32, TARGET_LONG_BITS - shamt));
+}
+
 static bool trans_slli_uw(DisasContext *ctx, arg_slli_uw *a)
 {
 REQUIRE_64BIT(ctx);
 REQUIRE_EXT(ctx, RVB);
-
-TCGv source1 = tcg_temp_new();
-gen_get_gpr(ctx, source1, a->rs1);
-
-if (a->shamt < 32) {
-tcg_gen_deposit_z_tl(source1, source1, a->shamt, 32);
-} else {
-tcg_gen_shli_tl(source1, source1, a->shamt);
-}
-
-gen_set_gpr(ctx, a->rd, source1);
-tcg_temp_free(source1);
-return true;
+return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_slli_uw);
 }
-- 
2.25.1