Re: [PATCH v5 24/24] target/riscv: Use {get,dest}_gpr for RVV
On Tue, Aug 24, 2021 at 6:13 AM Richard Henderson
wrote:
>
> Remove gen_get_gpr, as the function becomes unused.
>
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Alistair
> ---
> target/riscv/translate.c| 13 ++---
> target/riscv/insn_trans/trans_rvv.c.inc | 74 +++--
> 2 files changed, 26 insertions(+), 61 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index e44254e878..e356fc6c46 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -232,11 +232,6 @@ static TCGv get_gpr(DisasContext *ctx, int reg_num,
> DisasExtend ext)
> g_assert_not_reached();
> }
>
> -static void gen_get_gpr(DisasContext *ctx, TCGv t, int reg_num)
> -{
> -tcg_gen_mov_tl(t, get_gpr(ctx, reg_num, EXT_NONE));
> -}
> -
> static TCGv dest_gpr(DisasContext *ctx, int reg_num)
> {
> if (reg_num == 0 || ctx->w) {
> @@ -637,9 +632,11 @@ void riscv_translate_init(void)
> {
> int i;
>
> -/* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */
> -/* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */
> -/* registers, unless you specifically block reads/writes to reg 0 */
> +/*
> + * cpu_gpr[0] is a placeholder for the zero register. Do not use it.
> + * Use the gen_set_gpr and get_gpr helper functions when accessing regs,
> + * unless you specifically block reads/writes to reg 0.
> + */
> cpu_gpr[0] = NULL;
>
> for (i = 1; i < 32; i++) {
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index de580c493c..fa451938f1 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -27,27 +27,22 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
> return false;
> }
>
> -s2 = tcg_temp_new();
> -dst = tcg_temp_new();
> +s2 = get_gpr(ctx, a->rs2, EXT_ZERO);
> +dst = dest_gpr(ctx, a->rd);
>
> /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
> if (a->rs1 == 0) {
> /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
> s1 = tcg_constant_tl(RV_VLEN_MAX);
> } else {
> -s1 = tcg_temp_new();
> -gen_get_gpr(ctx, s1, a->rs1);
> +s1 = get_gpr(ctx, a->rs1, EXT_ZERO);
> }
> -gen_get_gpr(ctx, s2, a->rs2);
> gen_helper_vsetvl(dst, cpu_env, s1, s2);
> gen_set_gpr(ctx, a->rd, dst);
> +
> tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
> lookup_and_goto_ptr(ctx);
> ctx->base.is_jmp = DISAS_NORETURN;
> -
> -tcg_temp_free(s1);
> -tcg_temp_free(s2);
> -tcg_temp_free(dst);
> return true;
> }
>
> @@ -60,23 +55,20 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli
> *a)
> }
>
> s2 = tcg_constant_tl(a->zimm);
> -dst = tcg_temp_new();
> +dst = dest_gpr(ctx, a->rd);
>
> /* Using x0 as the rs1 register specifier, encodes an infinite AVL */
> if (a->rs1 == 0) {
> /* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
> s1 = tcg_constant_tl(RV_VLEN_MAX);
> } else {
> -s1 = tcg_temp_new();
> -gen_get_gpr(ctx, s1, a->rs1);
> +s1 = get_gpr(ctx, a->rs1, EXT_ZERO);
> }
> gen_helper_vsetvl(dst, cpu_env, s1, s2);
> gen_set_gpr(ctx, a->rd, dst);
> +
> gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
> ctx->base.is_jmp = DISAS_NORETURN;
> -
> -tcg_temp_free(s1);
> -tcg_temp_free(dst);
> return true;
> }
>
> @@ -173,7 +165,7 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1,
> uint32_t data,
>
> dest = tcg_temp_new_ptr();
> mask = tcg_temp_new_ptr();
> -base = tcg_temp_new();
> +base = get_gpr(s, rs1, EXT_NONE);
>
> /*
> * As simd_desc supports at most 256 bytes, and in this implementation,
> @@ -184,7 +176,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1,
> uint32_t data,
> */
> desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
>
> -gen_get_gpr(s, base, rs1);
> tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
> tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
>
> @@ -192,7 +183,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1,
> uint32_t data,
>
> tcg_temp_free_ptr(dest);
> tcg_temp_free_ptr(mask);
> -tcg_temp_free(base);
> gen_set_label(over);
> return true;
> }
> @@ -330,12 +320,10 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t
> rs1, uint32_t rs2,
>
> dest = tcg_temp_new_ptr();
> mask = tcg_temp_new_ptr();
> -base = tcg_temp_new();
> -stride = tcg_temp_new();
> +base = get_gpr(s, rs1, EXT_NONE);
> +stride = get_gpr(s, rs2, EXT_NONE);
> desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
>
> -gen_get_gpr(s, base, rs1);
> -gen_get_gpr(s, stride, rs2);
> tcg_gen_addi_ptr(dest, cpu_env,
[PATCH v5 24/24] target/riscv: Use {get,dest}_gpr for RVV
Remove gen_get_gpr, as the function becomes unused.
Signed-off-by: Richard Henderson
---
target/riscv/translate.c| 13 ++---
target/riscv/insn_trans/trans_rvv.c.inc | 74 +++--
2 files changed, 26 insertions(+), 61 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index e44254e878..e356fc6c46 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -232,11 +232,6 @@ static TCGv get_gpr(DisasContext *ctx, int reg_num,
DisasExtend ext)
g_assert_not_reached();
}
-static void gen_get_gpr(DisasContext *ctx, TCGv t, int reg_num)
-{
-tcg_gen_mov_tl(t, get_gpr(ctx, reg_num, EXT_NONE));
-}
-
static TCGv dest_gpr(DisasContext *ctx, int reg_num)
{
if (reg_num == 0 || ctx->w) {
@@ -637,9 +632,11 @@ void riscv_translate_init(void)
{
int i;
-/* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */
-/* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */
-/* registers, unless you specifically block reads/writes to reg 0 */
+/*
+ * cpu_gpr[0] is a placeholder for the zero register. Do not use it.
+ * Use the gen_set_gpr and get_gpr helper functions when accessing regs,
+ * unless you specifically block reads/writes to reg 0.
+ */
cpu_gpr[0] = NULL;
for (i = 1; i < 32; i++) {
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index de580c493c..fa451938f1 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -27,27 +27,22 @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
return false;
}
-s2 = tcg_temp_new();
-dst = tcg_temp_new();
+s2 = get_gpr(ctx, a->rs2, EXT_ZERO);
+dst = dest_gpr(ctx, a->rd);
/* Using x0 as the rs1 register specifier, encodes an infinite AVL */
if (a->rs1 == 0) {
/* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
s1 = tcg_constant_tl(RV_VLEN_MAX);
} else {
-s1 = tcg_temp_new();
-gen_get_gpr(ctx, s1, a->rs1);
+s1 = get_gpr(ctx, a->rs1, EXT_ZERO);
}
-gen_get_gpr(ctx, s2, a->rs2);
gen_helper_vsetvl(dst, cpu_env, s1, s2);
gen_set_gpr(ctx, a->rd, dst);
+
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
lookup_and_goto_ptr(ctx);
ctx->base.is_jmp = DISAS_NORETURN;
-
-tcg_temp_free(s1);
-tcg_temp_free(s2);
-tcg_temp_free(dst);
return true;
}
@@ -60,23 +55,20 @@ static bool trans_vsetvli(DisasContext *ctx, arg_vsetvli *a)
}
s2 = tcg_constant_tl(a->zimm);
-dst = tcg_temp_new();
+dst = dest_gpr(ctx, a->rd);
/* Using x0 as the rs1 register specifier, encodes an infinite AVL */
if (a->rs1 == 0) {
/* As the mask is at least one bit, RV_VLEN_MAX is >= VLMAX */
s1 = tcg_constant_tl(RV_VLEN_MAX);
} else {
-s1 = tcg_temp_new();
-gen_get_gpr(ctx, s1, a->rs1);
+s1 = get_gpr(ctx, a->rs1, EXT_ZERO);
}
gen_helper_vsetvl(dst, cpu_env, s1, s2);
gen_set_gpr(ctx, a->rd, dst);
+
gen_goto_tb(ctx, 0, ctx->pc_succ_insn);
ctx->base.is_jmp = DISAS_NORETURN;
-
-tcg_temp_free(s1);
-tcg_temp_free(dst);
return true;
}
@@ -173,7 +165,7 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1,
uint32_t data,
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
-base = tcg_temp_new();
+base = get_gpr(s, rs1, EXT_NONE);
/*
* As simd_desc supports at most 256 bytes, and in this implementation,
@@ -184,7 +176,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1,
uint32_t data,
*/
desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-gen_get_gpr(s, base, rs1);
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -192,7 +183,6 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1,
uint32_t data,
tcg_temp_free_ptr(dest);
tcg_temp_free_ptr(mask);
-tcg_temp_free(base);
gen_set_label(over);
return true;
}
@@ -330,12 +320,10 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1,
uint32_t rs2,
dest = tcg_temp_new_ptr();
mask = tcg_temp_new_ptr();
-base = tcg_temp_new();
-stride = tcg_temp_new();
+base = get_gpr(s, rs1, EXT_NONE);
+stride = get_gpr(s, rs2, EXT_NONE);
desc = tcg_constant_i32(simd_desc(s->vlen / 8, s->vlen / 8, data));
-gen_get_gpr(s, base, rs1);
-gen_get_gpr(s, stride, rs2);
tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd));
tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0));
@@ -343,8 +331,6 @@ static bool ldst_stride_trans(uint32_t vd, uint32_t rs1,
uint32_t rs2,
tcg_temp_free_ptr(dest);
tcg_temp_free_ptr(mask);
-tcg_temp_free(base);
-tcg_temp_free(stride);
gen_set_label(over);
return true;
}
@@ -458,10 +444,9 @@ static bool
