Re: [PATCH v5 4/8] target/ppc: Implemented xvf*ger*
This patch is failing checkpatch.pl:
$ ../scripts/checkpatch.pl v5-4-8-target-ppc-Implemented-xvf-ger.patch
WARNING: line over 80 characters
#252: FILE: target/ppc/fpu_helper.c:3557:
+ vsxger_muladd_f mul, vsxger_muladd_f muladd, vsxger_zero
zero)
total: 0 errors, 1 warnings, 286 lines checked
v5-4-8-target-ppc-Implemented-xvf-ger.patch has style problems, please review.
If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
But more important, the patch doesn't apply in ppc-next
(gitlab.com/danielhb/qemu/tree/ppc-next)
and patch 01 doesn't apply on current QEMU master. Can you please re-send the
whole
series rebased on top of ppc-next?
Thanks,
Daniel
On 5/20/22 16:54, Lucas Mateus Castro(alqotel) wrote:
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
xvf32ger: VSX Vector 32-bit Floating-Point GER (rank-1 update)
xvf32gernn: VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative
multiply, Negative accumulate
xvf32gernp: VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative
multiply, Positive accumulate
xvf32gerpn: VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive
multiply, Negative accumulate
xvf32gerpp: VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive
multiply, Positive accumulate
xvf64ger: VSX Vector 64-bit Floating-Point GER (rank-1 update)
xvf64gernn: VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative
multiply, Negative accumulate
xvf64gernp: VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative
multiply, Positive accumulate
xvf64gerpn: VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive
multiply, Negative accumulate
xvf64gerpp: VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive
multiply, Positive accumulate
Signed-off-by: Lucas Mateus Castro (alqotel)
Reviewed-by: Richard Henderson
---
target/ppc/cpu.h| 4 +
target/ppc/fpu_helper.c | 193 +++-
target/ppc/helper.h | 10 ++
target/ppc/insn32.decode| 13 ++
target/ppc/translate/vsx-impl.c.inc | 12 ++
5 files changed, 230 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index c8a12a3985..bdedf4138e 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2641,6 +2641,8 @@ static inline bool lsw_reg_in_range(int start, int nregs,
int rx)
#define VsrSW(i) s32[i]
#define VsrD(i) u64[i]
#define VsrSD(i) s64[i]
+#define VsrSF(i) f32[i]
+#define VsrDF(i) f64[i]
#else
#define VsrB(i) u8[15 - (i)]
#define VsrSB(i) s8[15 - (i)]
@@ -2650,6 +2652,8 @@ static inline bool lsw_reg_in_range(int start, int nregs,
int rx)
#define VsrSW(i) s32[3 - (i)]
#define VsrD(i) u64[1 - (i)]
#define VsrSD(i) s64[1 - (i)]
+#define VsrSF(i) f32[3 - (i)]
+#define VsrDF(i) f64[1 - (i)]
#endif
static inline int vsr64_offset(int i, bool high)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 8592727792..1766da5bcf 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -414,7 +414,7 @@ void helper_store_fpscr(CPUPPCState *env, uint64_t val,
uint32_t nibbles)
ppc_store_fpscr(env, val);
}
-void helper_fpscr_check_status(CPUPPCState *env)
+static void do_fpscr_check_status(CPUPPCState *env, uintptr_t raddr)
{
CPUState *cs = env_cpu(env);
target_ulong fpscr = env->fpscr;
@@ -455,13 +455,19 @@ void helper_fpscr_check_status(CPUPPCState *env)
}
cs->exception_index = POWERPC_EXCP_PROGRAM;
env->error_code = error | POWERPC_EXCP_FP;
+env->fpscr |= error ? FP_FEX : 0;
/* Deferred floating-point exception after target FPSCR update */
if (fp_exceptions_enabled(env)) {
raise_exception_err_ra(env, cs->exception_index,
- env->error_code, GETPC());
+ env->error_code, raddr);
}
}
+void helper_fpscr_check_status(CPUPPCState *env)
+{
+do_fpscr_check_status(env, GETPC());
+}
+
static void do_float_check_status(CPUPPCState *env, bool change_fi,
uintptr_t raddr)
{
@@ -3469,3 +3475,186 @@ void helper_xssubqp(CPUPPCState *env, uint32_t opcode,
*xt = t;
do_float_check_status(env, true, GETPC());
}
+
+static inline void vsxger_excp(CPUPPCState *env, uintptr_t retaddr)
+{
+/*
+ * XV*GER instructions execute and set the FPSCR as if exceptions
+ * are disabled and only at the end throw an exception
+ */
+target_ulong enable;
+enable = env->fpscr & (FP_ENABLES | FP_FI | FP_FR);
+env->fpscr &= ~(FP_ENABLES | FP_FI | FP_FR);
+int status = get_float_exception_flags(>fp_status);
+if (unlikely(status & float_flag_invalid)) {
+if (status & float_flag_invalid_snan) {
+float_invalid_op_vxsnan(env, 0);
+}
+if (status & float_flag_invalid_imz) {
+
[PATCH v5 4/8] target/ppc: Implemented xvf*ger*
From: "Lucas Mateus Castro (alqotel)"
Implement the following PowerISA v3.1 instructions:
xvf32ger: VSX Vector 32-bit Floating-Point GER (rank-1 update)
xvf32gernn: VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative
multiply, Negative accumulate
xvf32gernp: VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative
multiply, Positive accumulate
xvf32gerpn: VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive
multiply, Negative accumulate
xvf32gerpp: VSX Vector 32-bit Floating-Point GER (rank-1 update) Positive
multiply, Positive accumulate
xvf64ger: VSX Vector 64-bit Floating-Point GER (rank-1 update)
xvf64gernn: VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative
multiply, Negative accumulate
xvf64gernp: VSX Vector 64-bit Floating-Point GER (rank-1 update) Negative
multiply, Positive accumulate
xvf64gerpn: VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive
multiply, Negative accumulate
xvf64gerpp: VSX Vector 64-bit Floating-Point GER (rank-1 update) Positive
multiply, Positive accumulate
Signed-off-by: Lucas Mateus Castro (alqotel)
Reviewed-by: Richard Henderson
---
target/ppc/cpu.h| 4 +
target/ppc/fpu_helper.c | 193 +++-
target/ppc/helper.h | 10 ++
target/ppc/insn32.decode| 13 ++
target/ppc/translate/vsx-impl.c.inc | 12 ++
5 files changed, 230 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index c8a12a3985..bdedf4138e 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2641,6 +2641,8 @@ static inline bool lsw_reg_in_range(int start, int nregs,
int rx)
#define VsrSW(i) s32[i]
#define VsrD(i) u64[i]
#define VsrSD(i) s64[i]
+#define VsrSF(i) f32[i]
+#define VsrDF(i) f64[i]
#else
#define VsrB(i) u8[15 - (i)]
#define VsrSB(i) s8[15 - (i)]
@@ -2650,6 +2652,8 @@ static inline bool lsw_reg_in_range(int start, int nregs,
int rx)
#define VsrSW(i) s32[3 - (i)]
#define VsrD(i) u64[1 - (i)]
#define VsrSD(i) s64[1 - (i)]
+#define VsrSF(i) f32[3 - (i)]
+#define VsrDF(i) f64[1 - (i)]
#endif
static inline int vsr64_offset(int i, bool high)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 8592727792..1766da5bcf 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -414,7 +414,7 @@ void helper_store_fpscr(CPUPPCState *env, uint64_t val,
uint32_t nibbles)
ppc_store_fpscr(env, val);
}
-void helper_fpscr_check_status(CPUPPCState *env)
+static void do_fpscr_check_status(CPUPPCState *env, uintptr_t raddr)
{
CPUState *cs = env_cpu(env);
target_ulong fpscr = env->fpscr;
@@ -455,13 +455,19 @@ void helper_fpscr_check_status(CPUPPCState *env)
}
cs->exception_index = POWERPC_EXCP_PROGRAM;
env->error_code = error | POWERPC_EXCP_FP;
+env->fpscr |= error ? FP_FEX : 0;
/* Deferred floating-point exception after target FPSCR update */
if (fp_exceptions_enabled(env)) {
raise_exception_err_ra(env, cs->exception_index,
- env->error_code, GETPC());
+ env->error_code, raddr);
}
}
+void helper_fpscr_check_status(CPUPPCState *env)
+{
+do_fpscr_check_status(env, GETPC());
+}
+
static void do_float_check_status(CPUPPCState *env, bool change_fi,
uintptr_t raddr)
{
@@ -3469,3 +3475,186 @@ void helper_xssubqp(CPUPPCState *env, uint32_t opcode,
*xt = t;
do_float_check_status(env, true, GETPC());
}
+
+static inline void vsxger_excp(CPUPPCState *env, uintptr_t retaddr)
+{
+/*
+ * XV*GER instructions execute and set the FPSCR as if exceptions
+ * are disabled and only at the end throw an exception
+ */
+target_ulong enable;
+enable = env->fpscr & (FP_ENABLES | FP_FI | FP_FR);
+env->fpscr &= ~(FP_ENABLES | FP_FI | FP_FR);
+int status = get_float_exception_flags(>fp_status);
+if (unlikely(status & float_flag_invalid)) {
+if (status & float_flag_invalid_snan) {
+float_invalid_op_vxsnan(env, 0);
+}
+if (status & float_flag_invalid_imz) {
+float_invalid_op_vximz(env, false, 0);
+}
+if (status & float_flag_invalid_isi) {
+float_invalid_op_vxisi(env, false, 0);
+}
+}
+do_float_check_status(env, false, retaddr);
+env->fpscr |= enable;
+do_fpscr_check_status(env, retaddr);
+}
+
+typedef void vsxger_zero(ppc_vsr_t *at, int, int);
+
+typedef void vsxger_muladd_f(ppc_vsr_t *, ppc_vsr_t *, ppc_vsr_t *, int, int,
+ int flags, float_status *s);
+
+static void vsxger_muladd32(ppc_vsr_t *at, ppc_vsr_t *a, ppc_vsr_t *b, int i,
+int j, int flags, float_status *s)
+{
+at[i].VsrSF(j) = float32_muladd(a->VsrSF(i), b->VsrSF(j),
+at[i].VsrSF(j), flags, s);
+}
+
+static void vsxger_mul32(ppc_vsr_t *at, ppc_vsr_t *a, ppc_vsr_t *b, int i,
+
