From: Matheus Ferst
Signed-off-by: Matheus Ferst
---
target/ppc/helper.h| 1 +
target/ppc/insn32.decode | 4 ++
target/ppc/int_helper.c| 62 ++
target/ppc/translate/fixedpoint-impl.c.inc | 12 +
4 files changed, 79 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index ea9f2a236c..c517b9f025 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -46,6 +46,7 @@ DEF_HELPER_4(divwe, tl, env, tl, tl, i32)
DEF_HELPER_FLAGS_1(popcntb, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_2(cmpb, TCG_CALL_NO_RWG_SE, tl, tl, tl)
DEF_HELPER_3(sraw, tl, env, tl, tl)
+DEF_HELPER_FLAGS_2(cfuged, TCG_CALL_NO_RWG_SE, i64, i64, i64)
#if defined(TARGET_PPC64)
DEF_HELPER_FLAGS_2(cmpeqb, TCG_CALL_NO_RWG_SE, i32, tl, tl)
DEF_HELPER_FLAGS_1(popcntw, TCG_CALL_NO_RWG_SE, tl, tl)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index bc69c70493..d4044d9069 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -87,6 +87,10 @@ STDUX 01 . . . 0010110101 - @X
ADDI001110 . . @D
ADDIS 00 . . @D
+## Fixed-Point Logical Instructions
+
+CFUGED 01 . . . 0011011100 - @X
+
### Move To/From System Register Instructions
SETBC 01 . . - 011000 - @X_bi
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 41f8477d4b..efa833ef64 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -320,6 +320,68 @@ target_ulong helper_popcntb(target_ulong val)
}
#endif
+uint64_t helper_cfuged(uint64_t src, uint64_t mask)
+{
+/*
+ * Instead of processing the mask bit-by-bit from the most significant to
+ * the least significant bit, as described in PowerISA, we'll handle it in
+ * blocks of 'n' zeros/ones from LSB to MSB. To avoid the decision to use
+ * ctz or cto, we negate the mask at the end of the loop.
+ */
+target_ulong m, left = 0, right = 0;
+unsigned int n, i = 64;
+bool bit = false; /* tracks if we are processing zeros or ones */
+
+if (mask == 0 || mask == -1) {
+return src;
+}
+
+/* Processes the mask in blocks, from LSB to MSB */
+while (i) {
+/* Find how many bits we should take */
+n = ctz64(mask);
+if (n > i) {
+n = i;
+}
+
+/*
+ * Extracts 'n' trailing bits of src and put them on the leading 'n'
+ * bits of 'right' or 'left', pushing down the previously extracted
+ * values.
+ */
+m = (1ll << n) - 1;
+if (bit) {
+right = ror64(right | (src & m), n);
+} else {
+left = ror64(left | (src & m), n);
+}
+
+/*
+ * Discards the processed bits from 'src' and 'mask'. Note that we are
+ * removing 'n' trailing zeros from 'mask', but the logical shift will
+ * add 'n' leading zeros back, so the population count of 'mask' is
kept
+ * the same.
+ */
+src >>= n;
+mask >>= n;
+i -= n;
+bit = !bit;
+mask = ~mask;
+}
+
+/*
+ * At the end, right was ror'ed ctpop(mask) times. To put it back in place,
+ * we'll shift it more 64-ctpop(mask) times.
+ */
+if (bit) {
+n = ctpop64(mask);
+} else {
+n = 64 - ctpop64(mask);
+}
+
+return left | (right >> n);
+}
+
/*/
/* PowerPC 601 specific instructions (POWER bridge) */
target_ulong helper_div(CPUPPCState *env, target_ulong arg1, target_ulong arg2)
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc
b/target/ppc/translate/fixedpoint-impl.c.inc
index 5f9845fa40..50933a3b9d 100644
--- a/target/ppc/translate/fixedpoint-impl.c.inc
+++ b/target/ppc/translate/fixedpoint-impl.c.inc
@@ -227,3 +227,15 @@ TRANS(SETBC, do_set_bool_cond, false, false)
TRANS(SETBCR, do_set_bool_cond, false, true)
TRANS(SETNBC, do_set_bool_cond, true, false)
TRANS(SETNBCR, do_set_bool_cond, true, true)
+
+static bool trans_CFUGED(DisasContext *ctx, arg_X *a)
+{
+REQUIRE_64BIT(ctx);
+REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+#if defined(TARGET_PPC64)
+gen_helper_cfuged(cpu_gpr[a->ra], cpu_gpr[a->rt], cpu_gpr[a->rb]);
+#else
+qemu_build_not_reached();
+#endif
+return true;
+}
--
2.25.1
