From: Matheus Ferst
Additionally, REQUIRE_64BIT when L=1 to match what is specified in The
Programming Environments Manual:
"For 32-bit implementations, the L field must be cleared, otherwise the
instruction form is invalid."
Some CPUs are known to deviate from this specification by ignoring the
L bit [1]. The stricter behavior, however, can help users that test
software with qemu, making it more likely to detect bugs that would
otherwise be silent.
If deemed necessary, a future patch can adapt this behavior based on
the specific CPU model.
[1] The 601 manual is the only one I've found that explicitly states
that the L bit is ignored, but we also observe this behavior in a 7447A
v1.2.
Signed-off-by: Matheus Ferst
---
target/ppc/insn32.decode | 14 ++
target/ppc/translate.c | 52 --
target/ppc/translate/fixedpoint-impl.c.inc | 33 +-
3 files changed, 46 insertions(+), 53 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 93e5d44d9e..9fd8d6b817 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -20,6 +20,10 @@
rt ra si:int64_t
@D .. rt:5 ra:5 si:s16
+_bf bf l:bool ra imm
+@D_bfs .. bf:3 - l:1 ra:5 imm:s16 _bf
+@D_bfu .. bf:3 - l:1 ra:5 imm:16 _bf
+
%ds_si 2:s14 !function=times_4
@DS .. rt:5 ra:5 .. .. si=%ds_si
@@ -36,6 +40,9 @@
_bi rt bi
@X_bi .. rt:5 bi:5 - .. - _bi
+_bfl bf l:bool ra rb
+@X_bfl .. bf:3 - l:1 ra:5 rb:5 ..- _bfl
+
### Fixed-Point Load Instructions
LBZ 100010 . . @D
@@ -89,6 +96,13 @@ STDU10 . . ..01 @DS
STDX01 . . . 0010010101 - @X
STDUX 01 . . . 0010110101 - @X
+### Fixed-Point Compare Instructions
+
+CMP 01 ... - . . . 00 - @X_bfl
+CMPL01 ... - . . . 10 - @X_bfl
+CMPI001011 ... - . . @D_bfs
+CMPLI 001010 ... - . . @D_bfu
+
### Fixed-Point Arithmetic Instructions
ADDI001110 . . @D
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 35d8831d44..95e4d9b815 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -1489,54 +1489,6 @@ static inline void gen_set_Rc0(DisasContext *ctx, TCGv
reg)
}
}
-/* cmp */
-static void gen_cmp(DisasContext *ctx)
-{
-if ((ctx->opcode & 0x0020) && (ctx->insns_flags & PPC_64B)) {
-gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
- 1, crfD(ctx->opcode));
-} else {
-gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
- 1, crfD(ctx->opcode));
-}
-}
-
-/* cmpi */
-static void gen_cmpi(DisasContext *ctx)
-{
-if ((ctx->opcode & 0x0020) && (ctx->insns_flags & PPC_64B)) {
-gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
-1, crfD(ctx->opcode));
-} else {
-gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
- 1, crfD(ctx->opcode));
-}
-}
-
-/* cmpl */
-static void gen_cmpl(DisasContext *ctx)
-{
-if ((ctx->opcode & 0x0020) && (ctx->insns_flags & PPC_64B)) {
-gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
- 0, crfD(ctx->opcode));
-} else {
-gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
- 0, crfD(ctx->opcode));
-}
-}
-
-/* cmpli */
-static void gen_cmpli(DisasContext *ctx)
-{
-if ((ctx->opcode & 0x0020) && (ctx->insns_flags & PPC_64B)) {
-gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
-0, crfD(ctx->opcode));
-} else {
-gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
- 0, crfD(ctx->opcode));
-}
-}
-
/* cmprb - range comparison: isupper, isaplha, islower*/
static void gen_cmprb(DisasContext *ctx)
{
@@ -7639,10 +7591,6 @@ GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0xF801,
PPC_NONE, PPC2_ISA310),
GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0xF801, PPC_NONE, PPC2_ISA310),
#endif
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0x, PPC_NONE),
-GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x0040, PPC_INTEGER),
-GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x0040, PPC_INTEGER),
-GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x0041, PPC_INTEGER),
-GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x0040, PPC_INTEGER),
#if defined(TARGET_PPC64)
GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x0060, PPC_NONE, PPC2_ISA300),
#endif
diff --git a/target/ppc/translate/fixedpoint-impl.c.inc
