Adding the high part of a very minimal set of csr. Signed-off-by: Frédéric Pétrot <frederic.pet...@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.por...@grenoble-inp.org> Reviewed-by: Richard Henderson <richard.hender...@linaro.org> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> --- target/riscv/cpu.h | 4 ++++ target/riscv/machine.c | 2 ++ 2 files changed, 6 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 603ae04837..a7c2e5c93e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -193,6 +193,10 @@ struct CPURISCVState { target_ulong hgatp; uint64_t htimedelta; + /* Upper 64-bits of 128-bit CSRs */ + uint64_t mscratchh; + uint64_t sscratchh; + /* Virtual CSRs */ /* * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 8af9caabf5..13b9ab375b 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -179,6 +179,8 @@ static const VMStateDescription vmstate_rv128 = { .needed = rv128_needed, .fields = (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32), + VMSTATE_UINT64(env.mscratchh, RISCVCPU), + VMSTATE_UINT64(env.sscratchh, RISCVCPU), VMSTATE_END_OF_LIST() } }; -- 2.34.0