Re: [PATCH v6 23/61] target/riscv: vector integer merge and move instructions

2020-03-27 Thread Richard Henderson 
On 3/17/20 8:06 AM, LIU Zhiwei wrote:
> +if (s->vl_eq_vlmax) {
> +#ifdef TARGET_RISCV64
> +tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
> + MAXSZ(s), MAXSZ(s), s1);
> +#else
> +tcg_gen_gvec_dup_i32(s->sew, vreg_ofs(s, a->rd),
> + MAXSZ(s), MAXSZ(s), s1);
> +#endif

Note to self: Add tcg_gen_gvec_dup_tl to tcg-op-gvec.h.

> +switch (s->sew) {
> +case 0:
> +tcg_gen_gvec_dup8i(vreg_ofs(s, a->rd),
> +   MAXSZ(s), MAXSZ(s), simm);
> +break;
> +case 1:
> +tcg_gen_gvec_dup16i(vreg_ofs(s, a->rd),
> +MAXSZ(s), MAXSZ(s), simm);
> +break;
> +case 2:
> +tcg_gen_gvec_dup32i(vreg_ofs(s, a->rd),
> +MAXSZ(s), MAXSZ(s), simm);
> +break;
> +default:
> +tcg_gen_gvec_dup64i(vreg_ofs(s, a->rd),
> +MAXSZ(s), MAXSZ(s), simm);
> +break;
> +}

Note to self: Add tcg_gen_gvec_dup_imm(vece, ...).

Neither are your problem, but we should remember to update this code.

Reviewed-by: Richard Henderson 


r~

Re: [PATCH v6 23/61] target/riscv: vector integer merge and move instructions

2020-03-26 Thread Alistair Francis 
On Tue, Mar 17, 2020 at 8:53 AM LIU Zhiwei  wrote:
>
> Signed-off-by: LIU Zhiwei 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/helper.h   |  17 
>  target/riscv/insn32.decode  |   7 ++
>  target/riscv/insn_trans/trans_rvv.inc.c | 121 
>  target/riscv/vector_helper.c| 100 
>  4 files changed, 245 insertions(+)
>
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 1f0d3d60e3..f378db9cbf 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -665,3 +665,20 @@ DEF_HELPER_6(vwmaccsu_vx_w, void, ptr, ptr, tl, ptr, 
> env, i32)
>  DEF_HELPER_6(vwmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32)
>  DEF_HELPER_6(vwmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32)
>  DEF_HELPER_6(vwmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32)
> +
> +DEF_HELPER_6(vmerge_vvm_b, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vmerge_vvm_h, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vmerge_vvm_w, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vmerge_vvm_d, void, ptr, ptr, ptr, ptr, env, i32)
> +DEF_HELPER_6(vmerge_vxm_b, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vmerge_vxm_h, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vmerge_vxm_w, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_6(vmerge_vxm_d, void, ptr, ptr, tl, ptr, env, i32)
> +DEF_HELPER_4(vmv_v_v_b, void, ptr, ptr, env, i32)
> +DEF_HELPER_4(vmv_v_v_h, void, ptr, ptr, env, i32)
> +DEF_HELPER_4(vmv_v_v_w, void, ptr, ptr, env, i32)
> +DEF_HELPER_4(vmv_v_v_d, void, ptr, ptr, env, i32)
> +DEF_HELPER_4(vmv_v_x_b, void, ptr, i64, env, i32)
> +DEF_HELPER_4(vmv_v_x_h, void, ptr, i64, env, i32)
> +DEF_HELPER_4(vmv_v_x_w, void, ptr, i64, env, i32)
> +DEF_HELPER_4(vmv_v_x_d, void, ptr, i64, env, i32)
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 9735ac3565..adb76956c9 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -71,6 +71,7 @@
>  @r_nfvm  ... ... vm:1 . . ... . ...  %nf %rs2 %rs1 %rd
>  @r_vm.. vm:1 . . ... . ...  %rs2 %rs1 %rd
>  @r_vm_1  .. . . . ... . ... vm=1 %rs2 %rs1 %rd
> +@r_vm_0  .. . . . ... . ... vm=0 %rs2 %rs1 %rd
>  @r_wdvm  . wd:1 vm:1 . . ... . ...  %rs2 %rs1 %rd
>  @r2_zimm . zimm:11  . ... . ... %rs1 %rd
>
> @@ -400,6 +401,12 @@ vwmacc_vx   01 . . . 110 . 1010111 
> @r_vm
>  vwmaccsu_vv 10 . . . 010 . 1010111 @r_vm
>  vwmaccsu_vx 10 . . . 110 . 1010111 @r_vm
>  vwmaccus_vx 11 . . . 110 . 1010111 @r_vm
> +vmv_v_v 010111 1 0 . 000 . 1010111 @r2
> +vmv_v_x 010111 1 0 . 100 . 1010111 @r2
> +vmv_v_i 010111 1 0 . 011 . 1010111 @r2
> +vmerge_vvm  010111 0 . . 000 . 1010111 @r_vm_0
> +vmerge_vxm  010111 0 . . 100 . 1010111 @r_vm_0
> +vmerge_vim  010111 0 . . 011 . 1010111 @r_vm_0
>
>  vsetvli 0 ... . 111 . 1010111  @r2_zimm
>  vsetvl  100 . . 111 . 1010111  @r
> diff --git a/target/riscv/insn_trans/trans_rvv.inc.c 
> b/target/riscv/insn_trans/trans_rvv.inc.c
> index 269d04c7fb..42ef59364f 100644
> --- a/target/riscv/insn_trans/trans_rvv.inc.c
> +++ b/target/riscv/insn_trans/trans_rvv.inc.c
> @@ -1499,3 +1499,124 @@ GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx)
>  GEN_OPIVX_WIDEN_TRANS(vwmacc_vx)
>  GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx)
>  GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx)
> +
> +/* Vector Integer Merge and Move Instructions */
> +static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
> +{
> +if (vext_check_isa_ill(s) &&
> +vext_check_reg(s, a->rd, false) &&
> +vext_check_reg(s, a->rs1, false)) {
> +
> +if (s->vl_eq_vlmax) {
> +tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd),
> + vreg_ofs(s, a->rs1),
> + MAXSZ(s), MAXSZ(s));
> +} else {
> +uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
> +static gen_helper_gvec_2_ptr * const fns[4] = {
> +gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
> +gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
> +};
> +
> +tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
> +   cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
> +}
> +return true;
> +}
> +return false;
> +}
> +
> +typedef void gen_helper_vmv_vx(TCGv_ptr, TCGv_i64, TCGv_env, TCGv_i32);
> +static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
> +{
> +if (vext_check_isa_ill(s) &&
> +vext_check_reg(s, a->rd, false)) {
> +
> +TCGv s1 = tcg_temp_new();
> +gen_get_gpr(s1, a->rs1);
> +
> +if (s->vl_eq_vlmax) {
> +#ifdef TARGET_RISCV64
> +

[PATCH v6 23/61] target/riscv: vector integer merge and move instructions

2020-03-17 Thread LIU Zhiwei 
Signed-off-by: LIU Zhiwei 
---
 target/riscv/helper.h   |  17 
 target/riscv/insn32.decode  |   7 ++
 target/riscv/insn_trans/trans_rvv.inc.c | 121 
 target/riscv/vector_helper.c| 100 
 4 files changed, 245 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 1f0d3d60e3..f378db9cbf 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -665,3 +665,20 @@ DEF_HELPER_6(vwmaccsu_vx_w, void, ptr, ptr, tl, ptr, env, 
i32)
 DEF_HELPER_6(vwmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vwmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32)
 DEF_HELPER_6(vwmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vmerge_vvm_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmerge_vvm_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmerge_vvm_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmerge_vvm_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmerge_vxm_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmerge_vxm_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmerge_vxm_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmerge_vxm_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_4(vmv_v_v_b, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vmv_v_v_h, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vmv_v_v_w, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vmv_v_v_d, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vmv_v_x_b, void, ptr, i64, env, i32)
+DEF_HELPER_4(vmv_v_x_h, void, ptr, i64, env, i32)
+DEF_HELPER_4(vmv_v_x_w, void, ptr, i64, env, i32)
+DEF_HELPER_4(vmv_v_x_d, void, ptr, i64, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 9735ac3565..adb76956c9 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -71,6 +71,7 @@
 @r_nfvm  ... ... vm:1 . . ... . ...  %nf %rs2 %rs1 %rd
 @r_vm.. vm:1 . . ... . ...  %rs2 %rs1 %rd
 @r_vm_1  .. . . . ... . ... vm=1 %rs2 %rs1 %rd
+@r_vm_0  .. . . . ... . ... vm=0 %rs2 %rs1 %rd
 @r_wdvm  . wd:1 vm:1 . . ... . ...  %rs2 %rs1 %rd
 @r2_zimm . zimm:11  . ... . ... %rs1 %rd
 
@@ -400,6 +401,12 @@ vwmacc_vx   01 . . . 110 . 1010111 
@r_vm
 vwmaccsu_vv 10 . . . 010 . 1010111 @r_vm
 vwmaccsu_vx 10 . . . 110 . 1010111 @r_vm
 vwmaccus_vx 11 . . . 110 . 1010111 @r_vm
+vmv_v_v 010111 1 0 . 000 . 1010111 @r2
+vmv_v_x 010111 1 0 . 100 . 1010111 @r2
+vmv_v_i 010111 1 0 . 011 . 1010111 @r2
+vmerge_vvm  010111 0 . . 000 . 1010111 @r_vm_0
+vmerge_vxm  010111 0 . . 100 . 1010111 @r_vm_0
+vmerge_vim  010111 0 . . 011 . 1010111 @r_vm_0
 
 vsetvli 0 ... . 111 . 1010111  @r2_zimm
 vsetvl  100 . . 111 . 1010111  @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c 
b/target/riscv/insn_trans/trans_rvv.inc.c
index 269d04c7fb..42ef59364f 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1499,3 +1499,124 @@ GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx)
 GEN_OPIVX_WIDEN_TRANS(vwmacc_vx)
 GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx)
 GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx)
+
+/* Vector Integer Merge and Move Instructions */
+static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
+{
+if (vext_check_isa_ill(s) &&
+vext_check_reg(s, a->rd, false) &&
+vext_check_reg(s, a->rs1, false)) {
+
+if (s->vl_eq_vlmax) {
+tcg_gen_gvec_mov(s->sew, vreg_ofs(s, a->rd),
+ vreg_ofs(s, a->rs1),
+ MAXSZ(s), MAXSZ(s));
+} else {
+uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
+static gen_helper_gvec_2_ptr * const fns[4] = {
+gen_helper_vmv_v_v_b, gen_helper_vmv_v_v_h,
+gen_helper_vmv_v_v_w, gen_helper_vmv_v_v_d,
+};
+
+tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs1),
+   cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
+}
+return true;
+}
+return false;
+}
+
+typedef void gen_helper_vmv_vx(TCGv_ptr, TCGv_i64, TCGv_env, TCGv_i32);
+static bool trans_vmv_v_x(DisasContext *s, arg_vmv_v_x *a)
+{
+if (vext_check_isa_ill(s) &&
+vext_check_reg(s, a->rd, false)) {
+
+TCGv s1 = tcg_temp_new();
+gen_get_gpr(s1, a->rs1);
+
+if (s->vl_eq_vlmax) {
+#ifdef TARGET_RISCV64
+tcg_gen_gvec_dup_i64(s->sew, vreg_ofs(s, a->rd),
+ MAXSZ(s), MAXSZ(s), s1);
+#else
+tcg_gen_gvec_dup_i32(s->sew, vreg_ofs(s, a->rd),
+ MAXSZ(s), MAXSZ(s), s1);
+#endif
+} else {
+TCGv_i32 desc;
+