Re: [PATCH v8 00/45] target/arm: Implement ARMv8.5-MemTag, system mode
On Tue, 23 Jun 2020 at 20:37, Richard Henderson wrote: > > Version 8 incorporates quite a bit of review (thanks, PMM): > > * Include HCR_DCT in the HCR_EL2 update. > * Use a separate decode function for ADDG/SUBG. > * Use the system arm_cpu_do_unaligned_access for user-only as well. > * Fix alignment for LDG. > * Fix no-fault for mte_probe1. > * Rearrage how tagged pages are recorded. I think I've reviewed everything that didn't already have review now. thanks -- PMM
Re: [PATCH v8 00/45] target/arm: Implement ARMv8.5-MemTag, system mode
Patchew URL: https://patchew.org/QEMU/20200623193658.623279-1-richard.hender...@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Subject: [PATCH v8 00/45] target/arm: Implement ARMv8.5-MemTag, system mode Type: series Message-id: 20200623193658.623279-1-richard.hender...@linaro.org === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === From https://github.com/patchew-project/qemu * [new tag] patchew/20200623193658.623279-1-richard.hender...@linaro.org -> patchew/20200623193658.623279-1-richard.hender...@linaro.org Switched to a new branch 'test' 1231ec5 target/arm: Enable MTE caf48f0 target/arm: Add allocation tag storage for system mode 86926ba target/arm: Create tagged ram when MTE is enabled dc24d39 target/arm: Cache the Tagged bit for a page in MemTxAttrs b3fdcfe target/arm: Always pass cacheattr to get_phys_addr 52dae54 target/arm: Set PSTATE.TCO on exception entry 9d92dcf target/arm: Implement data cache set allocation tags 985b40f target/arm: Complete TBI clearing for user-only for SVE d22a925 target/arm: Add mte helpers for sve scatter/gather memory ops 26d1ba5 target/arm: Handle TBI for sve scalar + int memory ops 5dc33b2 target/arm: Add mte helpers for sve scalar + int ff/nf loads 457edf5 target/arm: Add mte helpers for sve scalar + int stores 7e68033 target/arm: Add mte helpers for sve scalar + int loads df0ee49 target/arm: Add arm_tlb_bti_gp 46870d1 target/arm: Tidy trans_LD1R_zpri 661859f target/arm: Use mte_check1 for sve LD1R c067218 target/arm: Use mte_checkN for sve unpredicated stores abbc5d1 target/arm: Use mte_checkN for sve unpredicated loads da2c53d target/arm: Add helper_mte_check_zva a947bd3 target/arm: Implement helper_mte_checkN 017e09e target/arm: Implement helper_mte_check1 060a546 target/arm: Add gen_mte_checkN 349cca3 target/arm: Add gen_mte_check1 bcb99d2 target/arm: Move regime_tcr to internals.h 3e1b548 target/arm: Move regime_el to internals.h e03f1b4 target/arm: Implement the access tag cache flushes d6ad4b5 target/arm: Implement the LDGM, STGM, STZGM instructions e16594d target/arm: Simplify DC_ZVA dc1d79a target/arm: Restrict the values of DCZID.BS under TCG 1291525 target/arm: Implement the STGP instruction 1b4d84d target/arm: Implement LDG, STG, ST2G instructions 54c306b target/arm: Define arm_cpu_do_unaligned_access for user-only 56adc0c target/arm: Implement the SUBP instruction e1d7cf7 target/arm: Implement the GMI instruction 2890f30 target/arm: Implement the ADDG, SUBG instructions 912b9bf target/arm: Revise decoding for disas_add_sub_imm 63945d2 target/arm: Implement the IRG instruction 22de2b3 target/arm: Add MTE bits to tb_flags 45f22ac target/arm: Add MTE system registers 2fbb1da target/arm: Add DISAS_UPDATE_NOCHAIN e4d0611 target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT d0f228b target/arm: Add support for MTE to HCR_EL2 and SCR_EL3 a5b3055 target/arm: Add support for MTE to SCTLR_ELx abdfb70 target/arm: Improve masking of SCR RES0 bits 40707f0 target/arm: Add isar tests for mte === OUTPUT BEGIN === 1/45 Checking commit 40707f09f121 (target/arm: Add isar tests for mte) 2/45 Checking commit abdfb70dea3d (target/arm: Improve masking of SCR RES0 bits) 3/45 Checking commit a5b305518974 (target/arm: Add support for MTE to SCTLR_ELx) 4/45 Checking commit d0f228b9f5f4 (target/arm: Add support for MTE to HCR_EL2 and SCR_EL3) 5/45 Checking commit e4d06118aebc (target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT) 6/45 Checking commit 2fbb1dafd99c (target/arm: Add DISAS_UPDATE_NOCHAIN) 7/45 Checking commit 45f22acdd599 (target/arm: Add MTE system registers) 8/45 Checking commit 22de2b35721f (target/arm: Add MTE bits to tb_flags) 9/45 Checking commit 63945d282302 (target/arm: Implement the IRG instruction) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #45: new file mode 100644 total: 0 errors, 1 warnings, 120 lines checked Patch 9/45 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 10/45 Checking commit 912b9bf152c9 (target/arm: Revise decoding for disas_add_sub_imm) 11/45 Checking commit 2890f308b67c (target/arm: Implement the ADDG, SUBG instructions) 12/45 Checking commit e1d7cf7b3195 (target/arm: Implement the GMI instruction) 13/45 Checking commit 56adc0c58443 (target/arm: Implement the SUBP instruction) 14/45 Checking commit 54c306b84778 (target/arm: Define arm_cpu_do_unaligned_access for user-only) 15/45 Checking commit 1b4d84d4bf40 (target/arm: Implement LDG, STG, ST2G instructions) 16/45 Checking commit 129152540330 (target/arm: Implement the STGP instruction) 17/45 Checking commit dc1d79a46ea9 (target/arm: Restrict the values of DCZID.BS
Re: [PATCH v8 00/45] target/arm: Implement ARMv8.5-MemTag, system mode
On 6/23/20 12:55 PM, Derrick McKee wrote: > Hi Richard, > > I am currently doing research with MTE, and Arm's FVP leaves a lot to > be desired. Is there some way I can get access to your QEMU changes > that enable MTE for system emulation? Thanks. You can apply this patch set to qemu master. ;-) But more seriously, this patch set is in the tree at https://github.com/rth7680/qemu/tree/tgt-arm-mte r~ > > On Tue, Jun 23, 2020 at 3:37 PM Richard Henderson > wrote: >> >> Version 8 incorporates quite a bit of review (thanks, PMM): >> >> * Include HCR_DCT in the HCR_EL2 update. >> * Use a separate decode function for ADDG/SUBG. >> * Use the system arm_cpu_do_unaligned_access for user-only as well. >> * Fix alignment for LDG. >> * Fix no-fault for mte_probe1. >> * Rearrage how tagged pages are recorded. >> >> and perhaps most visibly, for those tracking the kernel patches: >> >> * Add arm,armv8.5-memtag to the dtb.
Re: [PATCH v8 00/45] target/arm: Implement ARMv8.5-MemTag, system mode
Hi Richard, I am currently doing research with MTE, and Arm's FVP leaves a lot to be desired. Is there some way I can get access to your QEMU changes that enable MTE for system emulation? Thanks. On Tue, Jun 23, 2020 at 3:37 PM Richard Henderson wrote: > > Version 8 incorporates quite a bit of review (thanks, PMM): > > * Include HCR_DCT in the HCR_EL2 update. > * Use a separate decode function for ADDG/SUBG. > * Use the system arm_cpu_do_unaligned_access for user-only as well. > * Fix alignment for LDG. > * Fix no-fault for mte_probe1. > * Rearrage how tagged pages are recorded. > > and perhaps most visibly, for those tracking the kernel patches: > > * Add arm,armv8.5-memtag to the dtb. > > > r~ > > > In need of review: > 0010-target-arm-Revise-decoding-for-disas_add_sub_imm.patch > 0011-target-arm-Implement-the-ADDG-SUBG-instructions.patch > 0014-target-arm-Define-arm_cpu_do_unaligned_access-for.patch > 0015-target-arm-Implement-LDG-STG-ST2G-instructions.patch > 0025-target-arm-Implement-helper_mte_check1.patch > 0028-target-arm-Use-mte_checkN-for-sve-unpredicated-lo.patch > 0029-target-arm-Use-mte_checkN-for-sve-unpredicated-st.patch > 0030-target-arm-Use-mte_check1-for-sve-LD1R.patch > 0031-target-arm-Tidy-trans_LD1R_zpri.patch > 0032-target-arm-Add-arm_tlb_bti_gp.patch > 0033-target-arm-Add-mte-helpers-for-sve-scalar-int-loa.patch > 0034-target-arm-Add-mte-helpers-for-sve-scalar-int-sto.patch > 0035-target-arm-Add-mte-helpers-for-sve-scalar-int-ff-.patch > 0036-target-arm-Handle-TBI-for-sve-scalar-int-memory-o.patch > 0037-target-arm-Add-mte-helpers-for-sve-scatter-gather.patch > 0038-target-arm-Complete-TBI-clearing-for-user-only-fo.patch > 0041-target-arm-Always-pass-cacheattr-to-get_phys_addr.patch > 0042-target-arm-Cache-the-Tagged-bit-for-a-page-in-Mem.patch > 0043-target-arm-Create-tagged-ram-when-MTE-is-enabled.patch > 0044-target-arm-Add-allocation-tag-storage-for-system-.patch > 0045-target-arm-Enable-MTE.patch > > > Richard Henderson (45): > target/arm: Add isar tests for mte > target/arm: Improve masking of SCR RES0 bits > target/arm: Add support for MTE to SCTLR_ELx > target/arm: Add support for MTE to HCR_EL2 and SCR_EL3 > target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT > target/arm: Add DISAS_UPDATE_NOCHAIN > target/arm: Add MTE system registers > target/arm: Add MTE bits to tb_flags > target/arm: Implement the IRG instruction > target/arm: Revise decoding for disas_add_sub_imm > target/arm: Implement the ADDG, SUBG instructions > target/arm: Implement the GMI instruction > target/arm: Implement the SUBP instruction > target/arm: Define arm_cpu_do_unaligned_access for user-only > target/arm: Implement LDG, STG, ST2G instructions > target/arm: Implement the STGP instruction > target/arm: Restrict the values of DCZID.BS under TCG > target/arm: Simplify DC_ZVA > target/arm: Implement the LDGM, STGM, STZGM instructions > target/arm: Implement the access tag cache flushes > target/arm: Move regime_el to internals.h > target/arm: Move regime_tcr to internals.h > target/arm: Add gen_mte_check1 > target/arm: Add gen_mte_checkN > target/arm: Implement helper_mte_check1 > target/arm: Implement helper_mte_checkN > target/arm: Add helper_mte_check_zva > target/arm: Use mte_checkN for sve unpredicated loads > target/arm: Use mte_checkN for sve unpredicated stores > target/arm: Use mte_check1 for sve LD1R > target/arm: Tidy trans_LD1R_zpri > target/arm: Add arm_tlb_bti_gp > target/arm: Add mte helpers for sve scalar + int loads > target/arm: Add mte helpers for sve scalar + int stores > target/arm: Add mte helpers for sve scalar + int ff/nf loads > target/arm: Handle TBI for sve scalar + int memory ops > target/arm: Add mte helpers for sve scatter/gather memory ops > target/arm: Complete TBI clearing for user-only for SVE > target/arm: Implement data cache set allocation tags > target/arm: Set PSTATE.TCO on exception entry > target/arm: Always pass cacheattr to get_phys_addr > target/arm: Cache the Tagged bit for a page in MemTxAttrs > target/arm: Create tagged ram when MTE is enabled > target/arm: Add allocation tag storage for system mode > target/arm: Enable MTE > > include/hw/arm/boot.h |3 + > target/arm/cpu.h | 50 +- > target/arm/helper-a64.h| 16 + > target/arm/helper-sve.h| 488 > target/arm/helper.h|2 + > target/arm/internals.h | 153 +++- > target/arm/translate-a64.h |5 + > target/arm/translate.h | 23 +- > hw/arm/boot.c | 12 +- > hw/arm/virt.c | 57 +- > target/arm/cpu.c | 77 +- > target/arm/cpu64.c |1 + > target/arm/helper-a64.c| 94 +-- > target/arm/helper.c| 423 +++--- > target/arm/m_helper.c | 11 +- > target/arm/mte_helper.c| 901 + >
[PATCH v8 00/45] target/arm: Implement ARMv8.5-MemTag, system mode
Version 8 incorporates quite a bit of review (thanks, PMM): * Include HCR_DCT in the HCR_EL2 update. * Use a separate decode function for ADDG/SUBG. * Use the system arm_cpu_do_unaligned_access for user-only as well. * Fix alignment for LDG. * Fix no-fault for mte_probe1. * Rearrage how tagged pages are recorded. and perhaps most visibly, for those tracking the kernel patches: * Add arm,armv8.5-memtag to the dtb. r~ In need of review: 0010-target-arm-Revise-decoding-for-disas_add_sub_imm.patch 0011-target-arm-Implement-the-ADDG-SUBG-instructions.patch 0014-target-arm-Define-arm_cpu_do_unaligned_access-for.patch 0015-target-arm-Implement-LDG-STG-ST2G-instructions.patch 0025-target-arm-Implement-helper_mte_check1.patch 0028-target-arm-Use-mte_checkN-for-sve-unpredicated-lo.patch 0029-target-arm-Use-mte_checkN-for-sve-unpredicated-st.patch 0030-target-arm-Use-mte_check1-for-sve-LD1R.patch 0031-target-arm-Tidy-trans_LD1R_zpri.patch 0032-target-arm-Add-arm_tlb_bti_gp.patch 0033-target-arm-Add-mte-helpers-for-sve-scalar-int-loa.patch 0034-target-arm-Add-mte-helpers-for-sve-scalar-int-sto.patch 0035-target-arm-Add-mte-helpers-for-sve-scalar-int-ff-.patch 0036-target-arm-Handle-TBI-for-sve-scalar-int-memory-o.patch 0037-target-arm-Add-mte-helpers-for-sve-scatter-gather.patch 0038-target-arm-Complete-TBI-clearing-for-user-only-fo.patch 0041-target-arm-Always-pass-cacheattr-to-get_phys_addr.patch 0042-target-arm-Cache-the-Tagged-bit-for-a-page-in-Mem.patch 0043-target-arm-Create-tagged-ram-when-MTE-is-enabled.patch 0044-target-arm-Add-allocation-tag-storage-for-system-.patch 0045-target-arm-Enable-MTE.patch Richard Henderson (45): target/arm: Add isar tests for mte target/arm: Improve masking of SCR RES0 bits target/arm: Add support for MTE to SCTLR_ELx target/arm: Add support for MTE to HCR_EL2 and SCR_EL3 target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT target/arm: Add DISAS_UPDATE_NOCHAIN target/arm: Add MTE system registers target/arm: Add MTE bits to tb_flags target/arm: Implement the IRG instruction target/arm: Revise decoding for disas_add_sub_imm target/arm: Implement the ADDG, SUBG instructions target/arm: Implement the GMI instruction target/arm: Implement the SUBP instruction target/arm: Define arm_cpu_do_unaligned_access for user-only target/arm: Implement LDG, STG, ST2G instructions target/arm: Implement the STGP instruction target/arm: Restrict the values of DCZID.BS under TCG target/arm: Simplify DC_ZVA target/arm: Implement the LDGM, STGM, STZGM instructions target/arm: Implement the access tag cache flushes target/arm: Move regime_el to internals.h target/arm: Move regime_tcr to internals.h target/arm: Add gen_mte_check1 target/arm: Add gen_mte_checkN target/arm: Implement helper_mte_check1 target/arm: Implement helper_mte_checkN target/arm: Add helper_mte_check_zva target/arm: Use mte_checkN for sve unpredicated loads target/arm: Use mte_checkN for sve unpredicated stores target/arm: Use mte_check1 for sve LD1R target/arm: Tidy trans_LD1R_zpri target/arm: Add arm_tlb_bti_gp target/arm: Add mte helpers for sve scalar + int loads target/arm: Add mte helpers for sve scalar + int stores target/arm: Add mte helpers for sve scalar + int ff/nf loads target/arm: Handle TBI for sve scalar + int memory ops target/arm: Add mte helpers for sve scatter/gather memory ops target/arm: Complete TBI clearing for user-only for SVE target/arm: Implement data cache set allocation tags target/arm: Set PSTATE.TCO on exception entry target/arm: Always pass cacheattr to get_phys_addr target/arm: Cache the Tagged bit for a page in MemTxAttrs target/arm: Create tagged ram when MTE is enabled target/arm: Add allocation tag storage for system mode target/arm: Enable MTE include/hw/arm/boot.h |3 + target/arm/cpu.h | 50 +- target/arm/helper-a64.h| 16 + target/arm/helper-sve.h| 488 target/arm/helper.h|2 + target/arm/internals.h | 153 +++- target/arm/translate-a64.h |5 + target/arm/translate.h | 23 +- hw/arm/boot.c | 12 +- hw/arm/virt.c | 57 +- target/arm/cpu.c | 77 +- target/arm/cpu64.c |1 + target/arm/helper-a64.c| 94 +-- target/arm/helper.c| 423 +++--- target/arm/m_helper.c | 11 +- target/arm/mte_helper.c| 901 + target/arm/op_helper.c | 16 + target/arm/sve_helper.c| 616 +++--- target/arm/tlb_helper.c| 13 +- target/arm/translate-a64.c | 652 +-- target/arm/translate-sve.c | 1366 +--- target/arm/translate-vfp.inc.c |2 +- target/arm/translate.c | 16 +- target/arm/Makefile.objs |1 + 24 files changed, 4164 insertions(+), 834 deletions(-) create mode
