Re: [PULL 00/15] target-arm queue

2022-07-18 Thread Peter Maydell 
On Mon, 18 Jul 2022 at 14:59, Peter Maydell  wrote:
>
> Some arm patches before softfreeze. These are all bug fixes.
>
> -- PMM
>
> The following changes since commit 0ebf76aae58324b8f7bf6af798696687f5f4c2a9:
>
>   Merge tag 'nvme-next-pull-request' of git://git.infradead.org/qemu-nvme 
> into staging (2022-07-15 15:38:13 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20220718
>
> for you to fetch changes up to 004c8a8bc569c8b18fca6fc90ffe3223daaf17b7:
>
>   Align Raspberry Pi DMA interrupts with Linux DTS (2022-07-18 13:25:13 +0100)
>
> 
> target-arm queue:
>  * hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held high
>  * target/arm: Fill in VL for tbflags when SME enabled and SVE disabled
>  * target/arm: Fix aarch64_sve_change_el for SME
>  * linux-user/aarch64: Do not clear PROT_MTE on mprotect
>  * target/arm: Honour VTCR_EL2 bits in Secure EL2
>  * hw/adc: Fix CONV bit in NPCM7XX ADC CON register
>  * hw/adc: Make adci[*] R/W in NPCM7XX ADC
>  * target/arm: Don't set syndrome ISS for loads and stores with writeback
>  * Align Raspberry Pi DMA interrupts with Linux DTS
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/7.1
for any user-visible changes.

-- PMM

[PULL 00/15] target-arm queue

2022-07-18 Thread Peter Maydell 
Some arm patches before softfreeze. These are all bug fixes.

-- PMM

The following changes since commit 0ebf76aae58324b8f7bf6af798696687f5f4c2a9:

  Merge tag 'nvme-next-pull-request' of git://git.infradead.org/qemu-nvme into 
staging (2022-07-15 15:38:13 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20220718

for you to fetch changes up to 004c8a8bc569c8b18fca6fc90ffe3223daaf17b7:

  Align Raspberry Pi DMA interrupts with Linux DTS (2022-07-18 13:25:13 +0100)


target-arm queue:
 * hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held high
 * target/arm: Fill in VL for tbflags when SME enabled and SVE disabled
 * target/arm: Fix aarch64_sve_change_el for SME
 * linux-user/aarch64: Do not clear PROT_MTE on mprotect
 * target/arm: Honour VTCR_EL2 bits in Secure EL2
 * hw/adc: Fix CONV bit in NPCM7XX ADC CON register
 * hw/adc: Make adci[*] R/W in NPCM7XX ADC
 * target/arm: Don't set syndrome ISS for loads and stores with writeback
 * Align Raspberry Pi DMA interrupts with Linux DTS


Andrey Makarov (1):
  Align Raspberry Pi DMA interrupts with Linux DTS

Hao Wu (2):
  hw/adc: Fix CONV bit in NPCM7XX ADC CON register
  hw/adc: Make adci[*] R/W in NPCM7XX ADC

Peter Maydell (9):
  hw/intc/armv7m_nvic: ICPRn must not unpend an IRQ that is being held high
  target/arm: Define and use new regime_tcr_value() function
  target/arm: Calculate mask/base_mask in get_level1_table_address()
  target/arm: Fold regime_tcr() and regime_tcr_value() together
  target/arm: Fix big-endian host handling of VTCR
  target/arm: Store VTCR_EL2, VSTCR_EL2 registers as uint64_t
  target/arm: Store TCR_EL* registers as uint64_t
  target/arm: Honour VTCR_EL2 bits in Secure EL2
  target/arm: Don't set syndrome ISS for loads and stores with writeback

Richard Henderson (3):
  target/arm: Fill in VL for tbflags when SME enabled and SVE disabled
  target/arm: Fix aarch64_sve_change_el for SME
  linux-user/aarch64: Do not clear PROT_MTE on mprotect

 include/hw/arm/bcm2835_peripherals.h |   2 +
 target/arm/cpu.h |  38 ---
 target/arm/internals.h   |  34 +++---
 accel/tcg/translate-all.c|  13 +++-
 hw/adc/npcm7xx_adc.c |   4 +-
 hw/arm/bcm2835_peripherals.c |  26 ++-
 hw/intc/armv7m_nvic.c|   9 ++-
 target/arm/cpu.c |   2 +-
 target/arm/debug_helper.c|   2 +-
 target/arm/helper.c  | 128 ---
 target/arm/ptw.c |  38 ++-
 target/arm/tlb_helper.c  |   2 +-
 target/arm/translate-a64.c   |   4 +-
 tests/qtest/bcm2835-dma-test.c   | 118 
 tests/qtest/npcm7xx_adc-test.c   |   2 +-
 tests/qtest/meson.build  |   3 +-
 16 files changed, 306 insertions(+), 119 deletions(-)
 create mode 100644 tests/qtest/bcm2835-dma-test.c

Re: [PULL 00/15] target-arm queue

2020-01-17 Thread Peter Maydell 
On Fri, 17 Jan 2020 at 14:28, Peter Maydell  wrote:
>
> Latest arm queue, a mixed bag of features and bug fixes.
>
> thanks
> -- PMM
>
> The following changes since commit cbf01142b2aef0c0b4e995cecd7e79d342bbc47e:
>
>   Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200115' into 
> staging (2020-01-17 12:13:17 +)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20200117-1
>
> for you to fetch changes up to 1a1fbc6cbb34c26d43d8360c66c1d21681af14a9:
>
>   target/arm: Set ISSIs16Bit in make_issinfo (2020-01-17 14:27:16 +)
>
> 
> Add model of the Netduino Plus 2 board
> Some allwinner-a10 code cleanup
> New test cases for cubieboard
> target/arm/arm-semi: fix SYS_OPEN to return nonzero filehandle
> i.MX: add an emulation for RNGC device
> target/arm: adjust program counter for wfi exception in AArch32
> arm/gicv3: update virtual irq state after IAR register read
> Set IL bit correctly for syndrome information for data aborts
>

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.0
for any user-visible changes.

-- PMM

[PULL 00/15] target-arm queue

2020-01-17 Thread Peter Maydell 
Latest arm queue, a mixed bag of features and bug fixes.

thanks
-- PMM

The following changes since commit cbf01142b2aef0c0b4e995cecd7e79d342bbc47e:

  Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20200115' into 
staging (2020-01-17 12:13:17 +)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20200117-1

for you to fetch changes up to 1a1fbc6cbb34c26d43d8360c66c1d21681af14a9:

  target/arm: Set ISSIs16Bit in make_issinfo (2020-01-17 14:27:16 +)


Add model of the Netduino Plus 2 board
Some allwinner-a10 code cleanup
New test cases for cubieboard
target/arm/arm-semi: fix SYS_OPEN to return nonzero filehandle
i.MX: add an emulation for RNGC device
target/arm: adjust program counter for wfi exception in AArch32
arm/gicv3: update virtual irq state after IAR register read
Set IL bit correctly for syndrome information for data aborts


Alistair Francis (4):
  hw/misc: Add the STM32F4xx Sysconfig device
  hw/misc: Add the STM32F4xx EXTI device
  hw/arm: Add the STM32F4xx SoC
  hw/arm: Add the Netduino Plus 2

Jeff Kubascik (3):
  target/arm: adjust program counter for wfi exception in AArch32
  arm/gicv3: update virtual irq state after IAR register read
  target/arm: Return correct IL bit in merge_syn_data_abort

Martin Kaiser (1):
  i.MX: add an emulation for RNGC

Masahiro Yamada (1):
  target/arm/arm-semi: fix SYS_OPEN to return nonzero filehandle

Philippe Mathieu-Daudé (5):
  tests/boot_linux_console: Add initrd test for the CubieBoard
  tests/boot_linux_console: Add a SD card test for the CubieBoard
  hw/arm/allwinner-a10: Move SoC definitions out of header
  hw/arm/allwinner-a10: Simplify by passing IRQs with qdev_pass_gpios()
  hw/arm/allwinner-a10: Remove local qemu_irq variables

Richard Henderson (1):
  target/arm: Set ISSIs16Bit in make_issinfo

 hw/arm/Makefile.objs   |   2 +
 hw/misc/Makefile.objs  |   3 +
 include/hw/arm/allwinner-a10.h |   7 -
 include/hw/arm/fsl-imx25.h |   5 +
 include/hw/arm/stm32f405_soc.h |  73 
 include/hw/misc/imx_rngc.h |  35 
 include/hw/misc/stm32f4xx_exti.h   |  60 +++
 include/hw/misc/stm32f4xx_syscfg.h |  61 +++
 hw/arm/allwinner-a10.c |  39 +++--
 hw/arm/fsl-imx25.c |  11 ++
 hw/arm/netduinoplus2.c |  52 ++
 hw/arm/stm32f405_soc.c | 302 +
 hw/intc/arm_gicv3_cpuif.c  |   3 +
 hw/misc/imx_rngc.c | 278 ++
 hw/misc/stm32f4xx_exti.c   | 188 
 hw/misc/stm32f4xx_syscfg.c | 171 +++
 target/arm/arm-semi.c  |   5 +-
 target/arm/op_helper.c |   7 +-
 target/arm/tlb_helper.c|   2 +-
 target/arm/translate.c |   3 +
 MAINTAINERS|  14 ++
 default-configs/arm-softmmu.mak|   1 +
 hw/arm/Kconfig |  10 ++
 hw/misc/Kconfig|   6 +
 hw/misc/trace-events   |  11 ++
 tests/acceptance/boot_linux_console.py |  85 ++
 26 files changed, 1405 insertions(+), 29 deletions(-)
 create mode 100644 include/hw/arm/stm32f405_soc.h
 create mode 100644 include/hw/misc/imx_rngc.h
 create mode 100644 include/hw/misc/stm32f4xx_exti.h
 create mode 100644 include/hw/misc/stm32f4xx_syscfg.h
 create mode 100644 hw/arm/netduinoplus2.c
 create mode 100644 hw/arm/stm32f405_soc.c
 create mode 100644 hw/misc/imx_rngc.c
 create mode 100644 hw/misc/stm32f4xx_exti.c
 create mode 100644 hw/misc/stm32f4xx_syscfg.c

Re: [Qemu-devel] [PULL 00/15] target-arm queue

2019-05-08 Thread Peter Maydell 
On Tue, 7 May 2019 at 13:00, Peter Maydell  wrote:
>
> A mixed bag, all bug fixes or similar small stuff.
>
> thanks
> -- PMM
>
>
> The following changes since commit 19eb2d4e736dc895f31fbd6b520e514f10cc08e0:
>
>   Merge remote-tracking branch 'remotes/thibault/tags/samuel-thibault' into 
> staging (2019-05-07 10:43:32 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20190507
>
> for you to fetch changes up to 63159601fb3e396b28da14cbb71e50ed3f5a0331:
>
>   target/arm: Stop using variable length array in dc_zva (2019-05-07 12:55:04 
> +0100)
>
> 


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/4.1
for any user-visible changes.

-- PMM

[Qemu-devel] [PULL 00/15] target-arm queue

2019-05-07 Thread Peter Maydell 
A mixed bag, all bug fixes or similar small stuff.

thanks
-- PMM


The following changes since commit 19eb2d4e736dc895f31fbd6b520e514f10cc08e0:

  Merge remote-tracking branch 'remotes/thibault/tags/samuel-thibault' into 
staging (2019-05-07 10:43:32 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20190507

for you to fetch changes up to 63159601fb3e396b28da14cbb71e50ed3f5a0331:

  target/arm: Stop using variable length array in dc_zva (2019-05-07 12:55:04 
+0100)


target-arm queue:
 * Stop using variable length array in dc_zva
 * Implement M-profile XPSR GE bits
 * Don't enable ARMV7M_EXCP_DEBUG from reset
 * armv7m_nvic: NS BFAR and BFSR are RAZ/WI if BFHFNMINS == 0
 * armv7m_nvic: Check subpriority in nvic_recompute_state_secure()
 * fix various minor issues to allow building for Windows-on-ARM64
 * aspeed: Set SDRAM size
 * Allow system registers for KVM guests to be changed by QEMU code
 * raspi: Diagnose requests for too much RAM
 * virt: Support firmware configuration with -blockdev


Cao Jiaxi (4):
  QEMU_PACKED: Remove gcc_struct attribute in Windows non x86 targets
  qga: Fix mingw compilation warnings on enum conversion
  util/cacheinfo: Use uint64_t on LLP64 model to satisfy Windows ARM64
  osdep: Fix mingw compilation regarding stdio formats

Joel Stanley (1):
  arm: aspeed: Set SDRAM size

Markus Armbruster (3):
  pc: Rearrange pc_system_firmware_init()'s legacy -drive loop
  pflash_cfi01: New pflash_cfi01_legacy_drive()
  hw/arm/virt: Support firmware configuration with -blockdev

Peter Maydell (7):
  hw/arm/raspi: Diagnose requests for too much RAM
  arm: Allow system registers for KVM guests to be changed by QEMU code
  hw/arm/armv7m_nvic: Check subpriority in nvic_recompute_state_secure()
  hw/intc/armv7m_nvic: NS BFAR and BFSR are RAZ/WI if BFHFNMINS == 0
  hw/intc/armv7m_nvic: Don't enable ARMV7M_EXCP_DEBUG from reset
  target/arm: Implement XPSR GE bits
  target/arm: Stop using variable length array in dc_zva

 contrib/libvhost-user/libvhost-user.h |   2 +-
 include/hw/arm/aspeed.h   |   1 +
 include/hw/arm/virt.h |   2 +
 include/hw/block/flash.h  |   1 +
 include/qemu/compiler.h   |   2 +-
 include/qemu/osdep.h  |  10 +-
 scripts/cocci-macro-file.h|   7 +-
 target/arm/cpu.h  |  13 ++-
 hw/arm/aspeed.c   |   8 ++
 hw/arm/raspi.c|   7 ++
 hw/arm/virt.c | 202 ++
 hw/block/pflash_cfi01.c   |  28 +
 hw/i386/pc_sysfw.c|  18 +--
 hw/intc/armv7m_nvic.c |  40 ++-
 qga/commands-win32.c  |   2 +-
 target/arm/helper.c   |  47 +++-
 target/arm/kvm.c  |   8 ++
 target/arm/kvm32.c|  20 +---
 target/arm/kvm64.c|   2 +
 target/arm/machine.c  |   2 +-
 util/cacheinfo.c  |   2 +-
 21 files changed, 294 insertions(+), 130 deletions(-)

Re: [Qemu-devel] [PULL 00/15] target-arm queue

2016-02-11 Thread Peter Maydell 
On 9 February 2016 at 18:42, Peter Maydell  wrote:
> Various things in this pull, but the one I care most about is that
> it includes the "enable EL3 for 64-bit CPUs" patches.
>
> thanks
> -- PMM
>
>
> The following changes since commit 84c0781103dcbe9b5e5433ba16fbeb55d69d6cb7:
>
>   Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2016-02-09' 
> into staging (2016-02-09 16:09:15 +)
>
> are available in the git repository at:
>
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20160209
>
> for you to fetch changes up to dfe1da1c1271dff825676435ff90da92cf4f:
>
>   bcm2835_property: implement "get board revision" query (2016-02-09 18:27:27 
> +)
>
> 
> target-arm queue:
>  * fix some missing traps for EL3 support
>  * enable EL3 on Cortex-A53 and Cortex-A57
>  * fix syndrome IL bit for Thumb coprocessor, VFP and Neon traps
>  * fix mishandling of architectural watchpoints
>  * avoid buffer overflow in sd.c
>  * fix max-cpus check in virt board
>  * implement 'get board revision' query for BCM2835

Ran into the "one of our compilers doesn't like typedef redefinitions" issue:
/home/petmay01/linaro/qemu-for-merges/include/qom/cpu.h:221: error:
redefinition of typedef ‘CPUWatchpoint’
/home/petmay01/linaro/qemu-for-merges/include/qom/cpu.h:67: error:
previous declaration of ‘CPUWatchpoint’ was here

Will do the trivial fix and resend:

diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 984bc8d..ff54600 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -211,14 +211,14 @@ typedef struct CPUBreakpoint {
 QTAILQ_ENTRY(CPUBreakpoint) entry;
 } CPUBreakpoint;

-typedef struct CPUWatchpoint {
+struct CPUWatchpoint {
 vaddr vaddr;
 vaddr len;
 vaddr hitaddr;
 MemTxAttrs hitattrs;
 int flags; /* BP_* */
 QTAILQ_ENTRY(CPUWatchpoint) entry;
-} CPUWatchpoint;
+};

 struct KVMState;
 struct kvm_run;

thanks
-- PMM

[Qemu-devel] [PULL 00/15] target-arm queue

2016-02-09 Thread Peter Maydell 
Various things in this pull, but the one I care most about is that
it includes the "enable EL3 for 64-bit CPUs" patches.

thanks
-- PMM


The following changes since commit 84c0781103dcbe9b5e5433ba16fbeb55d69d6cb7:

  Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2016-02-09' into 
staging (2016-02-09 16:09:15 +)

are available in the git repository at:


  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20160209

for you to fetch changes up to dfe1da1c1271dff825676435ff90da92cf4f:

  bcm2835_property: implement "get board revision" query (2016-02-09 18:27:27 
+)


target-arm queue:
 * fix some missing traps for EL3 support
 * enable EL3 on Cortex-A53 and Cortex-A57
 * fix syndrome IL bit for Thumb coprocessor, VFP and Neon traps
 * fix mishandling of architectural watchpoints
 * avoid buffer overflow in sd.c
 * fix max-cpus check in virt board
 * implement 'get board revision' query for BCM2835


Andrew Jones (1):
  hw/arm/virt: fix max-cpus check

Peter Maydell (10):
  target-arm: Fix typo in comment in arm_is_secure_below_el3()
  target-arm: Implement MDCR_EL3 and SDCR
  target-arm: Use access_trap_aa32s_el1() for SCR and MVBAR
  target-arm: Update arm_generate_debug_exceptions() to handle EL2/EL3
  target-arm: Add isread parameter to CPAccessFns
  target-arm: Implement NSACR trapping behaviour
  target-arm: Enable EL3 for Cortex-A53 and Cortex-A57
  target-arm: Correct misleading 'is_thumb' syn_* parameter names
  target-arm: Fix IL bit reported for Thumb coprocessor traps
  target-arm: Fix IL bit reported for Thumb VFP and Neon traps

Prasad J Pandit (1):
  sd: limit 'req.cmd' while using as an array index

Sergey Fedorov (2):
  cpu: Add callback to check architectural watchpoint match
  target-arm: Implement checking of fired watchpoint

Stephen Warren (1):
  bcm2835_property: implement "get board revision" query

 exec.c |   6 ++
 hw/arm/bcm2835_peripherals.c   |   2 +
 hw/arm/bcm2836.c   |   2 +
 hw/arm/raspi.c |   2 +
 hw/arm/virt.c  |  10 +--
 hw/misc/bcm2835_property.c |   4 +-
 hw/sd/sd.c |   7 +-
 include/hw/misc/bcm2835_property.h |   1 +
 include/qom/cpu.h  |   4 +
 qom/cpu.c  |   9 ++
 target-arm/cpu.c   |   1 +
 target-arm/cpu.h   |  55 ++--
 target-arm/cpu64.c |   2 +
 target-arm/helper.c| 173 +
 target-arm/helper.h|   2 +-
 target-arm/internals.h |  31 ---
 target-arm/op_helper.c |  40 +
 target-arm/translate-a64.c |   6 +-
 target-arm/translate.c |  21 +++--
 19 files changed, 286 insertions(+), 92 deletions(-)

Re: [Qemu-devel] [PULL 00/15] target-arm queue

2012-07-14 Thread Blue Swirl 
On Thu, Jul 12, 2012 at 1:36 PM, Peter Maydell peter.mayd...@linaro.org wrote:
 Usual target-arm pullreq. This one has a couple of bugfixes for
 issues in the cp15 rework, and the LPAE patch series (including
 switching to 64 bit physaddrs for ARM, and a trivial imx_avic
 patch which is needed as a prerequisite for that).

Thanks, pulled.


 thanks
 -- PMM

 The following changes since commit 92336855975805d88c7979f53bc05c2d47abab04:

   megasas: disable due to build breakage (2012-07-09 18:16:16 -0500)

 are available in the git repository at:
   git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream

 Paul Brook (1):
   target-arm: Fix CP15 based WFI

 Peter Maydell (14):
   target-arm: Fix typo that meant TTBR1 accesses went to TTBR0
   target-arm: Fix some copy-and-paste errors in cp register names
   target-arm: Fix TCG temp handling in 64 bit cp writes
   hw/imx_avic.c: Avoid format error when target_phys_addr_t is 64 bits
   ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bits
   target-arm: Implement privileged-execute-never (PXN)
   target-arm: Extend feature flags to 64 bits
   target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registers
   target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAE
   target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE
   target-arm: Use target_phys_addr_t in get_phys_addr()
   target-arm: Implement long-descriptor PAR format
   target-arm: Implement TTBCR changes for LPAE
   target-arm: Add support for long format translation table walks

  configure  |2 +-
  hw/imx_avic.c  |2 +-
  target-arm/cpu.c   |6 +-
  target-arm/cpu.h   |   15 +-
  target-arm/helper.c|  441 
 +++-
  target-arm/machine.c   |   10 +-
  target-arm/translate.c |4 +-
  7 files changed, 428 insertions(+), 52 deletions(-)

[Qemu-devel] [PULL 00/15] target-arm queue

2012-07-12 Thread Peter Maydell 
Usual target-arm pullreq. This one has a couple of bugfixes for
issues in the cp15 rework, and the LPAE patch series (including
switching to 64 bit physaddrs for ARM, and a trivial imx_avic
patch which is needed as a prerequisite for that).

thanks
-- PMM

The following changes since commit 92336855975805d88c7979f53bc05c2d47abab04:

  megasas: disable due to build breakage (2012-07-09 18:16:16 -0500)

are available in the git repository at:
  git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream

Paul Brook (1):
  target-arm: Fix CP15 based WFI

Peter Maydell (14):
  target-arm: Fix typo that meant TTBR1 accesses went to TTBR0
  target-arm: Fix some copy-and-paste errors in cp register names
  target-arm: Fix TCG temp handling in 64 bit cp writes
  hw/imx_avic.c: Avoid format error when target_phys_addr_t is 64 bits
  ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bits
  target-arm: Implement privileged-execute-never (PXN)
  target-arm: Extend feature flags to 64 bits
  target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registers
  target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAE
  target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE
  target-arm: Use target_phys_addr_t in get_phys_addr()
  target-arm: Implement long-descriptor PAR format
  target-arm: Implement TTBCR changes for LPAE
  target-arm: Add support for long format translation table walks

 configure  |2 +-
 hw/imx_avic.c  |2 +-
 target-arm/cpu.c   |6 +-
 target-arm/cpu.h   |   15 +-
 target-arm/helper.c|  441 +++-
 target-arm/machine.c   |   10 +-
 target-arm/translate.c |4 +-
 7 files changed, 428 insertions(+), 52 deletions(-)