Re: [PULL 00/32] riscv-to-apply queue
On 6/27/24 03:00, Alistair Francis wrote: The following changes since commit 3f044554b94fc0756d5b3cdbf84501e0eea0e629: Merge tag 'pull-vfio-20240624' ofhttps://github.com/legoater/qemu into staging (2024-06-24 21:30:34 -0700) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240627-1 for you to fetch changes up to 2f5a2315b84a9b1f089ecfc3f31b29813609a7b7: target/riscv: Apply modularized matching conditions for icount trigger (2024-06-27 13:09:16 +1000) RISC-V PR for 9.1 * Extend virtual irq csrs masks to be 64 bit wide * Move Guest irqs out of the core local irqs range * zvbb implies zvkb * virt: add address-cells in create_fdt_one_aplic() * virt: add aplic nodename helper * virt: rename aplic nodename to 'interrupt-controller' * virt: aplic DT: add 'qemu, aplic' to 'compatible' * virt: aplic DT: rename prop to 'riscv, delegation' * virt: change imsic nodename to 'interrupt-controller' * virt: imsics DT: add 'qemu, imsics' to 'compatible' * virt: imsics DT: add '#msi-cells' * QEMU support for KVM Guest Debug on RISC-V * Support RISC-V privilege 1.13 spec * Add support for RISC-V ACPI tests * Modularize common match conditions for trigger Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/9.1 as appropriate. r~
[PULL 00/32] riscv-to-apply queue
The following changes since commit 3f044554b94fc0756d5b3cdbf84501e0eea0e629: Merge tag 'pull-vfio-20240624' of https://github.com/legoater/qemu into staging (2024-06-24 21:30:34 -0700) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20240627-1 for you to fetch changes up to 2f5a2315b84a9b1f089ecfc3f31b29813609a7b7: target/riscv: Apply modularized matching conditions for icount trigger (2024-06-27 13:09:16 +1000) RISC-V PR for 9.1 * Extend virtual irq csrs masks to be 64 bit wide * Move Guest irqs out of the core local irqs range * zvbb implies zvkb * virt: add address-cells in create_fdt_one_aplic() * virt: add aplic nodename helper * virt: rename aplic nodename to 'interrupt-controller' * virt: aplic DT: add 'qemu, aplic' to 'compatible' * virt: aplic DT: rename prop to 'riscv, delegation' * virt: change imsic nodename to 'interrupt-controller' * virt: imsics DT: add 'qemu, imsics' to 'compatible' * virt: imsics DT: add '#msi-cells' * QEMU support for KVM Guest Debug on RISC-V * Support RISC-V privilege 1.13 spec * Add support for RISC-V ACPI tests * Modularize common match conditions for trigger Alvin Chang (3): target/riscv: Add functions for common matching conditions of trigger target/riscv: Apply modularized matching conditions for watchpoint target/riscv: Apply modularized matching conditions for icount trigger Branislav Brzak (1): target/riscv: Fix froundnx.h nanbox check Chao Du (3): target/riscv/kvm: add software breakpoints support target/riscv/kvm: handle the exit with debug reason target/riscv/kvm: define TARGET_KVM_HAVE_GUEST_DEBUG Clément Léger (1): target/riscv: fix instructions count handling in icount mode Daniel Henrique Barboza (8): hw/riscv/virt.c: add address-cells in create_fdt_one_aplic() hw/riscv/virt.c: add aplic nodename helper hw/riscv/virt.c: rename aplic nodename to 'interrupt-controller' hw/riscv/virt.c: aplic DT: add 'qemu, aplic' to 'compatible' hw/riscv/virt.c: aplic DT: rename prop to 'riscv, delegation' hw/riscv/virt.c: change imsic nodename to 'interrupt-controller' hw/riscv/virt.c: imsics DT: add 'qemu, imsics' to 'compatible' hw/riscv/virt.c: imsics DT: add '#msi-cells' Fea.Wang (5): target/riscv: Define macros and variables for ss1p13 target/riscv: Add 'P1P13' bit in SMSTATEEN0 target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32 target/riscv: Reserve exception codes for sw-check and hw-err target/riscv: Support the version for ss1p13 Frank Chang (6): target/riscv: Introduce extension implied rules definition target/riscv: Introduce extension implied rule helpers target/riscv: Add MISA extension implied rules target/riscv: Add multi extension implied rules target/riscv: Add Zc extension implied rule target/riscv: Remove extension auto-update check statements Jerry Zhang Jian (1): target/riscv: zvbb implies zvkb Jim Shu (1): target/riscv: Reuse the conversion function of priv_spec Rajnesh Kanwal (2): target/riscv: Extend virtual irq csrs masks to be 64 bit wide. target/riscv: Move Guest irqs out of the core local irqs range. Sunil V L (1): hw/riscv/virt.c: Make block devices default to virtio configs/targets/riscv64-softmmu.mak | 1 + include/hw/riscv/virt.h | 1 + target/riscv/cpu.h | 28 ++- target/riscv/cpu_bits.h | 8 +- target/riscv/cpu_cfg.h | 1 + hw/riscv/virt.c | 38 +++- target/riscv/cpu.c | 404 +++- target/riscv/csr.c | 92 ++-- target/riscv/debug.c| 129 target/riscv/fpu_helper.c | 2 +- target/riscv/kvm/kvm-cpu.c | 89 target/riscv/tcg/tcg-cpu.c | 287 ++--- 12 files changed, 877 insertions(+), 203 deletions(-)
Re: [PULL 00/32] riscv-to-apply queue
On Tue, 7 Feb 2023 at 07:12, Alistair Francis wrote: > > From: Alistair Francis > > The following changes since commit 6661b8c7fe3f8b5687d2d90f7b4f3f23d70e3e8b: > > Merge tag 'pull-ppc-20230205' of https://gitlab.com/danielhb/qemu into > staging (2023-02-05 16:49:09 +) > > are available in the Git repository at: > > https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230207 > > for you to fetch changes up to 5474aa4f3e0a3e9c171db7c55b5baf15f2e2778c: > > hw/riscv: virt: Simplify virt_{get,set}_aclint() (2023-02-07 08:21:32 +1000) > > > Third RISC-V PR for QEMU 8.0 > > * Update disas for xnor/orn/andn and slli.uw > * Update opentitan IRQs > * Fix rom code when Zicsr is disabled > * Update VS timer whenever htimedelta changes > * A collection of fixes for virtulisation > * Set tval for triggered watchpoints > * Cleanups for board and FDT creation > * Add support for the T-Head vendor extensions > * A fix for virtual instr exception > * Fix ctzw behavior > * Fix SBI getchar handler for KVM Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0 for any user-visible changes. -- PMM
[PULL 00/32] riscv-to-apply queue
From: Alistair Francis The following changes since commit 6661b8c7fe3f8b5687d2d90f7b4f3f23d70e3e8b: Merge tag 'pull-ppc-20230205' of https://gitlab.com/danielhb/qemu into staging (2023-02-05 16:49:09 +) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230207 for you to fetch changes up to 5474aa4f3e0a3e9c171db7c55b5baf15f2e2778c: hw/riscv: virt: Simplify virt_{get,set}_aclint() (2023-02-07 08:21:32 +1000) Third RISC-V PR for QEMU 8.0 * Update disas for xnor/orn/andn and slli.uw * Update opentitan IRQs * Fix rom code when Zicsr is disabled * Update VS timer whenever htimedelta changes * A collection of fixes for virtulisation * Set tval for triggered watchpoints * Cleanups for board and FDT creation * Add support for the T-Head vendor extensions * A fix for virtual instr exception * Fix ctzw behavior * Fix SBI getchar handler for KVM Alistair Francis (1): hw/riscv: boot: Don't use CSRs if they are disabled Anup Patel (4): target/riscv: Update VS timer whenever htimedelta changes target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX target/riscv: Ensure opcode is saved for all relevant instructions Bin Meng (1): hw/riscv: virt: Simplify virt_{get,set}_aclint() Christoph Müllner (14): RISC-V: Adding XTheadCmo ISA extension RISC-V: Adding XTheadSync ISA extension RISC-V: Adding XTheadBa ISA extension RISC-V: Adding XTheadBb ISA extension RISC-V: Adding XTheadBs ISA extension RISC-V: Adding XTheadCondMov ISA extension RISC-V: Adding T-Head multiply-accumulate instructions RISC-V: Adding T-Head MemPair extension RISC-V: Adding T-Head MemIdx extension RISC-V: Adding T-Head FMemIdx extension RISC-V: Set minimum priv version for Zfh to 1.11 RISC-V: Add initial support for T-Head C906 RISC-V: Adding XTheadFmv ISA extension target/riscv: add a MAINTAINERS entry for XThead* extension support Daniel Henrique Barboza (6): hw/riscv/virt.c: calculate socket count once in create_fdt_imsic() hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms' hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' hw/riscv/boot.c: calculate fdt size after fdt_pack() hw/riscv: split fdt address calculation from fdt load hw/riscv: change riscv_compute_fdt_addr() semantics Deepak Gupta (1): target/riscv: fix for virtual instr exception Philipp Tomsich (1): target/riscv: update disas.c for xnor/orn/andn and slli.uw Sergey Matyukevich (1): target/riscv: set tval for triggered watchpoints Vladimir Isaev (2): target/riscv: fix ctzw behavior target/riscv: fix SBI getchar handler for KVM Wilfred Mallawa (1): include/hw/riscv/opentitan: update opentitan IRQs MAINTAINERS |8 + include/hw/riscv/boot.h |4 +- include/hw/riscv/opentitan.h| 14 +- target/riscv/cpu.h | 12 + target/riscv/cpu_vendorid.h |6 + target/riscv/helper.h |1 + target/riscv/xthead.decode | 185 + disas/riscv.c |8 +- hw/riscv/boot.c | 62 +- hw/riscv/microchip_pfsoc.c |7 +- hw/riscv/opentitan.c| 80 +- hw/riscv/sifive_u.c |8 +- hw/riscv/spike.c| 25 +- hw/riscv/virt.c | 476 ++-- target/riscv/cpu.c | 55 +- target/riscv/cpu_helper.c |8 +- target/riscv/csr.c | 16 + target/riscv/debug.c|1 - target/riscv/kvm.c |5 +- target/riscv/op_helper.c|6 + target/riscv/time_helper.c | 36 +- target/riscv/translate.c| 32 + target/riscv/insn_trans/trans_rva.c.inc | 10 +- target/riscv/insn_trans/trans_rvb.c.inc |1 + target/riscv/insn_trans/trans_rvd.c.inc |2 + target/riscv/insn_trans/trans_rvf.c.inc |2 + target/riscv/insn_trans/trans_rvh.c.inc |3 + target/riscv/insn_trans/trans_rvi.c.inc |2 + target/riscv/insn_trans/trans_rvzfh.c.inc |2 + target/riscv/insn_trans/trans_svinval.c.inc |3 + target/riscv/insn_trans/trans_xthead.c.inc | 1094 +++ target/riscv/meson.build|1 + 32 files changed, 1847 insertions(+), 328 deletions(-) create mode 100644 target/riscv/cpu_vendorid.h create mode 100644 target/riscv/xthead.decode
Re: [PULL 00/32] riscv-to-apply queue
On Tue, 8 Jun 2021 at 01:30, Alistair Francis wrote: > > The following changes since commit a35947f15c0ee695eba3c55248ec8ac3e4e23cca: > > Merge remote-tracking branch > 'remotes/stsquad/tags/pull-testing-updates-070621-2' into staging (2021-06-07 > 15:45:48 +0100) > > are available in the Git repository at: > > g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210608-1 > > for you to fetch changes up to d2c1a177b138be35cb96216baa870c3564b123e4: > > target/riscv: rvb: add b-ext version cpu option (2021-06-08 09:59:46 +1000) > > > Second RISC-V PR for QEMU 6.1 > > - Update the PLIC and CLINT DT bindings > - Improve documentation for RISC-V machines > - Support direct kernel boot for microchip_pfsoc > - Fix WFI exception behaviour > - Improve CSR printing > - Initial support for the experimental Bit Manip extension > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/6.1 for any user-visible changes. -- PMM
[PULL 00/32] riscv-to-apply queue
The following changes since commit a35947f15c0ee695eba3c55248ec8ac3e4e23cca: Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-updates-070621-2' into staging (2021-06-07 15:45:48 +0100) are available in the Git repository at: g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20210608-1 for you to fetch changes up to d2c1a177b138be35cb96216baa870c3564b123e4: target/riscv: rvb: add b-ext version cpu option (2021-06-08 09:59:46 +1000) Second RISC-V PR for QEMU 6.1 - Update the PLIC and CLINT DT bindings - Improve documentation for RISC-V machines - Support direct kernel boot for microchip_pfsoc - Fix WFI exception behaviour - Improve CSR printing - Initial support for the experimental Bit Manip extension Alistair Francis (2): docs/system: Move the RISC-V -bios information to removed target/riscv/pmp: Add assert for ePMP operations Bin Meng (9): hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper hw/riscv: virt: Switch to use qemu_fdt_setprop_string_array() helper hw/riscv: Support the official CLINT DT bindings hw/riscv: Support the official PLIC DT bindings docs/system/riscv: Correct the indentation level of supported devices docs/system/riscv: sifive_u: Document '-dtb' usage hw/riscv: Use macros for BIOS image names hw/riscv: microchip_pfsoc: Support direct kernel boot target/riscv: Remove unnecessary riscv_*_names[] declaration Changbin Du (1): target/riscv: Dump CSR mscratch/sscratch/satp Frank Chang (6): target/riscv: rvb: count bits set target/riscv: add gen_shifti() and gen_shiftiw() helper functions target/riscv: rvb: single-bit instructions target/riscv: rvb: generalized reverse target/riscv: rvb: generalized or-combine target/riscv: rvb: add b-ext version cpu option Jose Martins (1): target/riscv: fix wfi exception behavior Kito Cheng (11): target/riscv: reformat @sh format encoding for B-extension target/riscv: rvb: count leading/trailing zeros target/riscv: rvb: logic-with-negate target/riscv: rvb: pack two words into one register target/riscv: rvb: min/max instructions target/riscv: rvb: sign-extend instructions target/riscv: rvb: shift ones target/riscv: rvb: rotate (left/right) target/riscv: rvb: address calculation target/riscv: rvb: add/shift with prefix zero-extend target/riscv: rvb: support and turn on B-extension from command line LIU Zhiwei (1): target/riscv: Pass the same value to oprsz and maxsz. Philippe Mathieu-Daudé (1): target/riscv: Do not include 'pmp.h' in user emulation docs/system/deprecated.rst | 19 -- docs/system/removed-features.rst | 5 + docs/system/riscv/microchip-icicle-kit.rst | 50 +++- docs/system/riscv/sifive_u.rst | 77 +++-- docs/system/target-riscv.rst | 13 +- include/hw/riscv/boot.h| 5 + target/riscv/cpu.h | 9 +- target/riscv/cpu_bits.h| 1 + target/riscv/helper.h | 6 + target/riscv/insn32.decode | 87 +- hw/riscv/microchip_pfsoc.c | 81 +- hw/riscv/sifive_u.c| 24 +- hw/riscv/spike.c | 12 +- hw/riscv/virt.c| 25 +- target/riscv/bitmanip_helper.c | 90 ++ target/riscv/cpu.c | 38 ++- target/riscv/op_helper.c | 11 +- target/riscv/pmp.c | 4 + target/riscv/translate.c | 306 target/riscv/insn_trans/trans_rvb.c.inc| 438 + target/riscv/insn_trans/trans_rvi.c.inc| 54 +--- target/riscv/insn_trans/trans_rvv.c.inc| 89 +++--- target/riscv/meson.build | 1 + 23 files changed, 1260 insertions(+), 185 deletions(-) create mode 100644 target/riscv/bitmanip_helper.c create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
Re: [PULL 00/32] riscv-to-apply queue
On Fri, Jun 19, 2020 at 5:37 AM Peter Maydell wrote: > > On Fri, 19 Jun 2020 at 07:34, Alistair Francis > wrote: > > > > The following changes since commit eefe34ea4b82c2b47abe28af4cc7247d51553626: > > > > Merge remote-tracking branch > > 'remotes/dgilbert/tags/pull-migration-20200617a' into staging (2020-06-18 > > 15:30:13 +0100) > > > > are available in the Git repository at: > > > > g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200618-1 > > > > for you to fetch changes up to fad6a8463510ff5e0fb31bb451a6c3218a45d179: > > > > hw/riscv: sifive_u: Add a dummy DDR memory controller device (2020-06-18 > > 23:09:16 -0700) > > > > > > This is a range of patches for RISC-V. > > > > Some key points are: > > - Generalise the CPU init functions > > - Support the SiFive revB machine > > - Improvements to the Hypervisor implementation and error checking > > - Connect some OpenTitan devices > > - Changes to the sifive_u machine to support U-boot > > > > > > Hi; I'm afraid this fails "make check": > > MALLOC_PERTURB_=${MALLOC_PERTURB_:-$(( ${RANDOM:-0} % 255 + 1))} > QTEST_QEMU_BINARY=riscv32-softmmu/qemu-system-riscv32 QTEST_QEM > U_IMG=qemu-img tests/qtest/qom-test -m=quick -k --tap < /dev/null | > ./scripts/tap-driver.pl --test-name="qom-test" > PASS 1 qom-test /riscv32/qom/opentitan > PASS 2 qom-test /riscv32/qom/spike > PASS 3 qom-test /riscv32/qom/virt > PASS 4 qom-test /riscv32/qom/none > qemu-system-riscv32: > /home/petmay01/linaro/qemu-for-merges/hw/core/qdev.c:438: > qdev_assert_realized_properly: Assertion `dev->parent_bus || > !dc->bus_type' failed. > Broken pipe > /home/petmay01/linaro/qemu-for-merges/tests/qtest/libqtest.c:175: > kill_qemu() detected QEMU death from signal 6 (Aborted) (core dumped) > > This is a recently introduced check that all devices created > get realized; probably somebody's added a new device in this > pullreq but forgot a realize call. Argh! The final rebase introduced this. Sorry, I'll send a v2. Alistair > > thanks > -- PMM
Re: [PULL 00/32] riscv-to-apply queue
On Fri, 19 Jun 2020 at 07:34, Alistair Francis wrote: > > The following changes since commit eefe34ea4b82c2b47abe28af4cc7247d51553626: > > Merge remote-tracking branch > 'remotes/dgilbert/tags/pull-migration-20200617a' into staging (2020-06-18 > 15:30:13 +0100) > > are available in the Git repository at: > > g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200618-1 > > for you to fetch changes up to fad6a8463510ff5e0fb31bb451a6c3218a45d179: > > hw/riscv: sifive_u: Add a dummy DDR memory controller device (2020-06-18 > 23:09:16 -0700) > > > This is a range of patches for RISC-V. > > Some key points are: > - Generalise the CPU init functions > - Support the SiFive revB machine > - Improvements to the Hypervisor implementation and error checking > - Connect some OpenTitan devices > - Changes to the sifive_u machine to support U-boot > > Hi; I'm afraid this fails "make check": MALLOC_PERTURB_=${MALLOC_PERTURB_:-$(( ${RANDOM:-0} % 255 + 1))} QTEST_QEMU_BINARY=riscv32-softmmu/qemu-system-riscv32 QTEST_QEM U_IMG=qemu-img tests/qtest/qom-test -m=quick -k --tap < /dev/null | ./scripts/tap-driver.pl --test-name="qom-test" PASS 1 qom-test /riscv32/qom/opentitan PASS 2 qom-test /riscv32/qom/spike PASS 3 qom-test /riscv32/qom/virt PASS 4 qom-test /riscv32/qom/none qemu-system-riscv32: /home/petmay01/linaro/qemu-for-merges/hw/core/qdev.c:438: qdev_assert_realized_properly: Assertion `dev->parent_bus || !dc->bus_type' failed. Broken pipe /home/petmay01/linaro/qemu-for-merges/tests/qtest/libqtest.c:175: kill_qemu() detected QEMU death from signal 6 (Aborted) (core dumped) This is a recently introduced check that all devices created get realized; probably somebody's added a new device in this pullreq but forgot a realize call. thanks -- PMM
Re: [PULL 00/32] riscv-to-apply queue
Patchew URL: https://patchew.org/QEMU/20200619062518.1718523-1-alistair.fran...@wdc.com/ Hi, This series failed the asan build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. === TEST SCRIPT BEGIN === #!/bin/bash export ARCH=x86_64 make docker-image-fedora V=1 NETWORK=1 time make docker-test-debug@fedora TARGET_LIST=x86_64-softmmu J=14 NETWORK=1 === TEST SCRIPT END === GEN docs/interop/qemu-ga-ref.html GEN docs/interop/qemu-ga-ref.txt GEN docs/interop/qemu-ga-ref.7 /usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o) /usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o) AS pc-bios/optionrom/multiboot.o AS pc-bios/optionrom/pvh.o AS pc-bios/optionrom/linuxboot.o --- SIGNpc-bios/optionrom/kvmvapic.bin LINKqemu-ga LINKqemu-keymap /usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o) LINKivshmem-client /usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o) LINKivshmem-server LINKqemu-nbd /usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o) /usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o) LINKqemu-storage-daemon LINKqemu-img /usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o) LINKqemu-io LINKqemu-edid /usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o) /usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o) LINKfsdev/virtfs-proxy-helper LINKscsi/qemu-pr-helper /usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o) LINKqemu-bridge-helper /usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o) /usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o) /usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o) LINKvirtiofsd /usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' overridden by definition from /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors.cpp.o) LINKvhost-user-input /usr/bin/ld: /usr/lib64/clang/10.0.0/lib/linux/libclang_rt.asan-x86_64.a(asan_interceptors_vfork.S.o): warning: common of `__interception::real_vfork' over
[PULL 00/32] riscv-to-apply queue
The following changes since commit eefe34ea4b82c2b47abe28af4cc7247d51553626: Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20200617a' into staging (2020-06-18 15:30:13 +0100) are available in the Git repository at: g...@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20200618-1 for you to fetch changes up to fad6a8463510ff5e0fb31bb451a6c3218a45d179: hw/riscv: sifive_u: Add a dummy DDR memory controller device (2020-06-18 23:09:16 -0700) This is a range of patches for RISC-V. Some key points are: - Generalise the CPU init functions - Support the SiFive revB machine - Improvements to the Hypervisor implementation and error checking - Connect some OpenTitan devices - Changes to the sifive_u machine to support U-boot Alistair Francis (11): sifive_e: Support the revB machine target/riscv: Set access as data_load when validating stage-2 PTEs target/riscv: Report errors validating 2nd-stage PTEs target/riscv: Move the hfence instructions to the rvh decode target/riscv: Implement checks for hfence riscv/opentitan: Fix the ROM size hw/char: Initial commit of Ibex UART hw/intc: Initial commit of lowRISC Ibex PLIC riscv/opentitan: Connect the PLIC device riscv/opentitan: Connect the UART device target/riscv: Use a smaller guess size for no-MMU PMP Bin Meng (20): riscv: Generalize CPU init routine for the base CPU riscv: Generalize CPU init routine for the gcsu CPU riscv: Generalize CPU init routine for the imacu CPU riscv: Keep the CPU init routine names consistent hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit hw/riscv: sifive_u: Generate device tree node for OTP hw/riscv: sifive_gpio: Clean up the codes hw/riscv: sifive_gpio: Add a new 'ngpio' property hw/riscv: sifive_u: Hook a GPIO controller hw/riscv: sifive_gpio: Do not blindly trigger output IRQs hw/riscv: sifive_u: Add reset functionality hw/riscv: sifive_u: Rename serial property get/set functions to a generic name hw/riscv: sifive_u: Add a new property msel for MSEL pin state target/riscv: Rename IBEX CPU init routine hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 hw/riscv: sifive_u: Support different boot source per MSEL pin state hw/riscv: sifive_u: Sort the SoC memmap table entries hw/riscv: sifive_u: Add a dummy DDR memory controller device Ian Jiang (1): riscv: Add helper to make NaN-boxing for FP register include/hw/char/ibex_uart.h| 110 ++ include/hw/intc/ibex_plic.h| 63 include/hw/riscv/opentitan.h | 16 + include/hw/riscv/sifive_e.h| 1 + include/hw/riscv/sifive_gpio.h | 8 +- include/hw/riscv/sifive_u.h| 27 ++ target/riscv/helper.h | 5 + target/riscv/insn32.decode | 8 +- hw/char/ibex_uart.c| 492 + hw/intc/ibex_plic.c| 261 + hw/riscv/opentitan.c | 71 +++- hw/riscv/sifive_e.c| 60 ++- hw/riscv/sifive_gpio.c | 45 ++- hw/riscv/sifive_u.c| 157 ++-- target/riscv/cpu.c | 69 ++-- target/riscv/cpu_helper.c | 9 +- target/riscv/insn_trans/trans_privileged.inc.c | 38 -- target/riscv/insn_trans/trans_rvf.inc.c| 17 +- target/riscv/insn_trans/trans_rvh.inc.c| 37 ++ target/riscv/op_helper.c | 13 + target/riscv/pmp.c | 14 +- target/riscv/translate.c | 1 + MAINTAINERS| 4 + hw/char/Makefile.objs | 1 + hw/intc/Makefile.objs | 1 + hw/riscv/Kconfig | 4 + 26 files changed, 1350 insertions(+), 182 deletions(-) create mode 100644 include/hw/char/ibex_uart.h create mode 100644 include/hw/intc/ibex_plic.h create mode 100644 hw/char/ibex_uart.c create mode 100644 hw/intc/ibex_plic.c create mode 100644 target/riscv/insn_trans/trans_rvh.inc.c