subject:"\[PULL 00\/42\] target\-arm queue"

Re: [PULL 00/42] target-arm queue

2023-06-06 Thread Richard Henderson


On 6/6/23 02:47, Peter Maydell wrote:

Hi; this pullreq includes FEAT_LSE2 support, the new
bpim2u board, and some other smaller patchsets.

thanks
-- PMM

The following changes since commit 369081c4558e7e940fa36ce59bf17b2e390f55d3:

   Merge tag 'pull-tcg-20230605' of https://gitlab.com/rth7680/qemu into 
staging (2023-06-05 13:16:56 -0700)

are available in the Git repository at:

   https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20230606

for you to fetch changes up to f9ac778898cb28307e0f91421aba34d43c34b679:

   target/arm: trap DCC access in user mode emulation (2023-06-06 10:19:40 
+0100)


target-arm queue:
  * Support gdbstub (guest debug) in HVF
  * xnlx-versal: Support CANFD controller
  * bpim2u: New board model: Banana Pi BPI-M2 Ultra
  * Emulate FEAT_LSE2
  * allow DC CVA[D]P in user mode emulation
  * trap DCC access in user mode emulation


Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/8.1 as 
appropriate.

I queued the reviewed ldst_atomicity.c.inc fix in front of this.

r~

[PULL 00/42] target-arm queue

2023-06-06 Thread Peter Maydell

Hi; this pullreq includes FEAT_LSE2 support, the new
bpim2u board, and some other smaller patchsets.

thanks
-- PMM

The following changes since commit 369081c4558e7e940fa36ce59bf17b2e390f55d3:

  Merge tag 'pull-tcg-20230605' of https://gitlab.com/rth7680/qemu into staging 
(2023-06-05 13:16:56 -0700)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20230606

for you to fetch changes up to f9ac778898cb28307e0f91421aba34d43c34b679:

  target/arm: trap DCC access in user mode emulation (2023-06-06 10:19:40 +0100)


target-arm queue:
 * Support gdbstub (guest debug) in HVF
 * xnlx-versal: Support CANFD controller
 * bpim2u: New board model: Banana Pi BPI-M2 Ultra
 * Emulate FEAT_LSE2
 * allow DC CVA[D]P in user mode emulation
 * trap DCC access in user mode emulation


Francesco Cagnin (4):
  arm: move KVM breakpoints helpers
  hvf: handle access for more registers
  hvf: add breakpoint handlers
  hvf: add guest debugging handlers for Apple Silicon hosts

Richard Henderson (20):
  target/arm: Add commentary for CPUARMState.exclusive_high
  target/arm: Add feature test for FEAT_LSE2
  target/arm: Introduce finalize_memop_{atom,pair}
  target/arm: Use tcg_gen_qemu_ld_i128 for LDXP
  target/arm: Use tcg_gen_qemu_{st, ld}_i128 for do_fp_{st, ld}
  target/arm: Use tcg_gen_qemu_st_i128 for STZG, STZ2G
  target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld, st}r
  target/arm: Sink gen_mte_check1 into load/store_exclusive
  target/arm: Load/store integer pair with one tcg operation
  target/arm: Hoist finalize_memop out of do_gpr_{ld, st}
  target/arm: Hoist finalize_memop out of do_fp_{ld, st}
  target/arm: Pass memop to gen_mte_check1*
  target/arm: Pass single_memop to gen_mte_checkN
  target/arm: Check alignment in helper_mte_check
  target/arm: Add SCTLR.nAA to TBFLAG_A64
  target/arm: Relax ordered/atomic alignment checks for LSE2
  target/arm: Move mte check for store-exclusive
  tests/tcg/aarch64: Use stz2g in mte-7.c
  tests/tcg/multiarch: Adjust sigbus.c
  target/arm: Enable FEAT_LSE2 for -cpu max

Vikram Garhwal (4):
  hw/net/can: Introduce Xilinx Versal CANFD controller
  xlnx-versal: Connect Xilinx VERSAL CANFD controllers
  MAINTAINERS: Include canfd tests under Xilinx CAN
  tests/qtest: Introduce tests for Xilinx VERSAL CANFD controller

Zhuojia Shen (3):
  target/arm: allow DC CVA[D]P in user mode emulation
  tests/tcg/aarch64: add DC CVA[D]P tests
  target/arm: trap DCC access in user mode emulation

qianfan Zhao (11):
  hw: arm: Add bananapi M2-Ultra and allwinner-r40 support
  hw/arm/allwinner-r40: add Clock Control Unit
  hw: allwinner-r40: Complete uart devices
  hw: arm: allwinner-r40: Add i2c0 device
  hw/misc: Rename axp209 to axp22x and add support AXP221 PMU
  hw/arm/allwinner-r40: add SDRAM controller device
  hw: sd: allwinner-sdhost: Add sun50i-a64 SoC support
  hw: arm: allwinner-r40: Add emac and gmac support
  hw: arm: allwinner-sramc: Add SRAM Controller support for R40
  tests: avocado: boot_linux_console: Add test case for bpim2u
  docs: system: arm: Introduce bananapi_m2u

 MAINTAINERS   |2 +-
 docs/system/arm/bananapi_m2u.rst  |  139 +++
 docs/system/arm/emulation.rst |1 +
 docs/system/arm/xlnx-versal-virt.rst  |   31 +
 docs/system/target-arm.rst|1 +
 include/hw/arm/allwinner-r40.h|  143 +++
 include/hw/arm/xlnx-versal.h  |   12 +
 include/hw/misc/allwinner-r40-ccu.h   |   65 +
 include/hw/misc/allwinner-r40-dramc.h |  108 ++
 include/hw/misc/allwinner-sramc.h |   69 ++
 include/hw/net/xlnx-versal-canfd.h|   87 ++
 include/hw/sd/allwinner-sdhost.h  |9 +
 include/sysemu/hvf.h  |   37 +
 include/sysemu/hvf_int.h  |2 +
 target/arm/cpu.h  |   16 +-
 target/arm/hvf_arm.h  |7 +
 target/arm/internals.h|   53 +-
 target/arm/tcg/helper-a64.h   |3 +
 target/arm/tcg/translate-a64.h|4 +-
 target/arm/tcg/translate.h|   65 +-
 accel/hvf/hvf-accel-ops.c |  119 ++
 accel/hvf/hvf-all.c   |   23 +
 hw/arm/allwinner-r40.c|  526 
 hw/arm/bananapi_m2u.c |  145 +++
 hw/arm/xlnx-versal-virt.c |   53 +
 hw/arm/xlnx-versal.c  |   37 +
 hw/misc/allwinner-r40-ccu.c   |  209 
 hw/misc/allwinner-r40-dramc.c |  513 
 hw/misc/allwinner-sramc.c |  184 +++
 hw/misc/axp209.c  |  238 
 hw/misc/axp2xx.c  |  283 +
 hw/net/can/xlnx-versal-canfd.c| 2107

Re: [PULL 00/42] target-arm queue

2020-06-24 Thread Peter Maydell

On Tue, 23 Jun 2020 at 12:39, Peter Maydell  wrote:
>
> The following changes since commit 61fee7f45955cd0bf9b79be9fa9c7ebabb5e6a85:
>
>   Merge remote-tracking branch 
> 'remotes/philmd-gitlab/tags/acceptance-testing-20200622' into staging 
> (2020-06-22 20:50:10 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20200623
>
> for you to fetch changes up to 539533b85fbd269f777bed931de8ccae1dd837e9:
>
>   arm/virt: Add memory hot remove support (2020-06-23 11:39:48 +0100)
>
> 
> target-arm queue:
>  * util/oslib-posix : qemu_init_exec_dir implementation for Mac
>  * target/arm: Last parts of neon decodetree conversion
>  * hw/arm/virt: Add 5.0 HW compat props
>  * hw/watchdog/cmsdk-apb-watchdog: Add trace event for lock status
>  * mps2: Add CMSDK APB watchdog, FPGAIO block, S2I devices and I2C devices
>  * mps2: Add some unimplemented-device stubs for audio and GPIO
>  * mps2-tz: Use the ARM SBCon two-wire serial bus interface
>  * target/arm: Check supported KVM features globally (not per vCPU)
>  * tests/qtest/arm-cpu-features: Add feature setting tests
>  * arm/virt: Add memory hot remove support


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.1
for any user-visible changes.

-- PMM

Re: [PULL 00/42] target-arm queue

2020-06-23 Thread no-reply

Patchew URL: 
https://patchew.org/QEMU/20200623113904.28805-1-peter.mayd...@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [PULL 00/42] target-arm queue
Type: series
Message-id: 20200623113904.28805-1-peter.mayd...@linaro.org

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

From https://github.com/patchew-project/qemu
 * [new tag] patchew/20200623113904.28805-1-peter.mayd...@linaro.org -> 
patchew/20200623113904.28805-1-peter.mayd...@linaro.org
Switched to a new branch 'test'
6bd9076 arm/virt: Add memory hot remove support
c668237 tests/qtest/arm-cpu-features: Add feature setting tests
4f01797 target/arm: Check supported KVM features globally (not per vCPU)
f9f6407 hw/arm/mps2-tz: Use the ARM SBCon two-wire serial bus interface
7d79ab3 hw/arm/mps2: Add audio I2S interface as unimplemented device
7f059c9 hw/arm/mps2: Add I2C devices
9af1079 hw/arm/mps2: Add SPI devices
4acc2b7 hw/arm/mps2: Map the FPGA I/O block
127d6ae hw/arm/mps2: Add CMSDK AHB GPIO peripherals as unimplemented devices
e32341b hw/arm/mps2: Add CMSDK APB watchdog device
6c17506 hw/arm/mps2: Rename CMSDK AHB peripheral region
ff60516 hw/arm/mps2: Document CMSDK/FPGA APB subsystem sections
24b7022 hw/arm: Use TYPE_VERSATILE_I2C instead of hardcoded string
0ff0e8b hw/i2c: Add header for ARM SBCon two-wire serial bus interface
c80e1d0 hw/i2c/versatile_i2c: Add SCL/SDA definitions
6abd95f hw/i2c/versatile_i2c: Add definitions for register addresses
ab757f4 hw/watchdog/cmsdk-apb-watchdog: Add trace event for lock status
16c5020 target/arm: Remove dead code relating to SABA and UABA
4cbe0e3 target/arm: Remove unnecessary gen_io_end() calls
9cdb63b target/arm: Move some functions used only in translate-neon.inc.c to 
that file
0d32b4f target/arm: Convert Neon VTRN to decodetree
41730a1 target/arm: Convert Neon VSWP to decodetree
0f0482a target/arm: Convert Neon 2-reg-misc VCVT insns to decodetree
d289839 target/arm: Convert Neon 2-reg-misc VRINT insns to decodetree
6169ea1 target/arm: Convert Neon 2-reg-misc fp-compare-with-zero insns to 
decodetree
945dde2 target/arm: Convert simple fp Neon 2-reg-misc insns
50c8ce6 target/arm: Convert Neon VQABS, VQNEG to decodetree
91f4194 target/arm: Convert remaining simple 2-reg-misc Neon ops
236fd32 target/arm: Convert Neon 2-reg-misc VREV32 and VREV16 to decodetree
17ce51c target/arm: Make gen_swap_half() take separate src and dest
5a24956 target/arm: Fix capitalization in NeonGenTwo{Single, Double}OPFn 
typedefs
60ac3ab target/arm: Rename NeonGenOneOpFn to NeonGenOne64OpFn
2139ddc target/arm: Convert Neon 2-reg-misc crypto operations to decodetree
8fe2e5f target/arm: Convert vectorised 2-reg-misc Neon ops to decodetree
0d3dc85 target/arm: Convert Neon VCVT f16/f32 insns to decodetree
6bfaec5 target/arm: Convert Neon 2-reg-misc VSHLL to decodetree
06ba9e4 target/arm: Convert Neon narrowing moves to decodetree
dba667b target/arm: Convert VZIP, VUZP to decodetree
7bb5bc9 target/arm: Convert Neon 2-reg-misc pairwise ops to decodetree
5c40ca4 target/arm: Convert Neon 2-reg-misc VREV64 to decodetree
6c9bf36 util/oslib-posix : qemu_init_exec_dir implementation for Mac
4d51f9a hw/arm/virt: Add 5.0 HW compat props

=== OUTPUT BEGIN ===
1/42 Checking commit 4d51f9a49a37 (hw/arm/virt: Add 5.0 HW compat props)
2/42 Checking commit 6c9bf36253e1 (util/oslib-posix : qemu_init_exec_dir 
implementation for Mac)
WARNING: architecture specific defines should be avoided
#28: FILE: util/oslib-posix.c:60:
+#ifdef __APPLE__

total: 0 errors, 1 warnings, 27 lines checked

Patch 2/42 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/42 Checking commit 5c40ca41aec8 (target/arm: Convert Neon 2-reg-misc VREV64 
to decodetree)
4/42 Checking commit 7bb5bc91f978 (target/arm: Convert Neon 2-reg-misc pairwise 
ops to decodetree)
5/42 Checking commit dba667b3b2b3 (target/arm: Convert VZIP, VUZP to decodetree)
6/42 Checking commit 06ba9e464f06 (target/arm: Convert Neon narrowing moves to 
decodetree)
7/42 Checking commit 6bfaec55c87e (target/arm: Convert Neon 2-reg-misc VSHLL to 
decodetree)
8/42 Checking commit 0d3dc85346e6 (target/arm: Convert Neon VCVT f16/f32 insns 
to decodetree)
9/42 Checking commit 8fe2e5f0c8b9 (target/arm: Convert vectorised 2-reg-misc 
Neon ops to decodetree)
10/42 Checking commit 2139ddc76378 (target/arm: Convert Neon 2-reg-misc crypto 
operations to decodetree)
11/42 Checking commit 60ac3ab2a6f4 (target/arm: Rename NeonGenOneOpFn to 
NeonGenOne64OpFn)
12/42 Checking commit 5a2495652793 (target/arm: Fix capitalization in 
NeonGenTwo{Single, Double}OPFn typedefs)
13/42 Checking commit 17ce51c555d4 (target/arm

[PULL 00/42] target-arm queue

2020-06-23 Thread Peter Maydell

The following changes since commit 61fee7f45955cd0bf9b79be9fa9c7ebabb5e6a85:

  Merge remote-tracking branch 
'remotes/philmd-gitlab/tags/acceptance-testing-20200622' into staging 
(2020-06-22 20:50:10 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20200623

for you to fetch changes up to 539533b85fbd269f777bed931de8ccae1dd837e9:

  arm/virt: Add memory hot remove support (2020-06-23 11:39:48 +0100)


target-arm queue:
 * util/oslib-posix : qemu_init_exec_dir implementation for Mac
 * target/arm: Last parts of neon decodetree conversion
 * hw/arm/virt: Add 5.0 HW compat props
 * hw/watchdog/cmsdk-apb-watchdog: Add trace event for lock status
 * mps2: Add CMSDK APB watchdog, FPGAIO block, S2I devices and I2C devices
 * mps2: Add some unimplemented-device stubs for audio and GPIO
 * mps2-tz: Use the ARM SBCon two-wire serial bus interface
 * target/arm: Check supported KVM features globally (not per vCPU)
 * tests/qtest/arm-cpu-features: Add feature setting tests
 * arm/virt: Add memory hot remove support


Andrew Jones (2):
  hw/arm/virt: Add 5.0 HW compat props
  tests/qtest/arm-cpu-features: Add feature setting tests

David CARLIER (1):
  util/oslib-posix : qemu_init_exec_dir implementation for Mac

Peter Maydell (23):
  target/arm: Convert Neon 2-reg-misc VREV64 to decodetree
  target/arm: Convert Neon 2-reg-misc pairwise ops to decodetree
  target/arm: Convert VZIP, VUZP to decodetree
  target/arm: Convert Neon narrowing moves to decodetree
  target/arm: Convert Neon 2-reg-misc VSHLL to decodetree
  target/arm: Convert Neon VCVT f16/f32 insns to decodetree
  target/arm: Convert vectorised 2-reg-misc Neon ops to decodetree
  target/arm: Convert Neon 2-reg-misc crypto operations to decodetree
  target/arm: Rename NeonGenOneOpFn to NeonGenOne64OpFn
  target/arm: Fix capitalization in NeonGenTwo{Single, Double}OPFn typedefs
  target/arm: Make gen_swap_half() take separate src and dest
  target/arm: Convert Neon 2-reg-misc VREV32 and VREV16 to decodetree
  target/arm: Convert remaining simple 2-reg-misc Neon ops
  target/arm: Convert Neon VQABS, VQNEG to decodetree
  target/arm: Convert simple fp Neon 2-reg-misc insns
  target/arm: Convert Neon 2-reg-misc fp-compare-with-zero insns to 
decodetree
  target/arm: Convert Neon 2-reg-misc VRINT insns to decodetree
  target/arm: Convert Neon 2-reg-misc VCVT insns to decodetree
  target/arm: Convert Neon VSWP to decodetree
  target/arm: Convert Neon VTRN to decodetree
  target/arm: Move some functions used only in translate-neon.inc.c to that 
file
  target/arm: Remove unnecessary gen_io_end() calls
  target/arm: Remove dead code relating to SABA and UABA

Philippe Mathieu-Daudé (15):
  hw/watchdog/cmsdk-apb-watchdog: Add trace event for lock status
  hw/i2c/versatile_i2c: Add definitions for register addresses
  hw/i2c/versatile_i2c: Add SCL/SDA definitions
  hw/i2c: Add header for ARM SBCon two-wire serial bus interface
  hw/arm: Use TYPE_VERSATILE_I2C instead of hardcoded string
  hw/arm/mps2: Document CMSDK/FPGA APB subsystem sections
  hw/arm/mps2: Rename CMSDK AHB peripheral region
  hw/arm/mps2: Add CMSDK APB watchdog device
  hw/arm/mps2: Add CMSDK AHB GPIO peripherals as unimplemented devices
  hw/arm/mps2: Map the FPGA I/O block
  hw/arm/mps2: Add SPI devices
  hw/arm/mps2: Add I2C devices
  hw/arm/mps2: Add audio I2S interface as unimplemented device
  hw/arm/mps2-tz: Use the ARM SBCon two-wire serial bus interface
  target/arm: Check supported KVM features globally (not per vCPU)

Shameer Kolothum (1):
  arm/virt: Add memory hot remove support

 include/hw/i2c/arm_sbcon_i2c.h   |   35 ++
 target/arm/cpu.h |2 +-
 target/arm/kvm_arm.h |   21 +-
 target/arm/translate.h   |8 +-
 target/arm/neon-dp.decode|  106 
 hw/acpi/generic_event_device.c   |   29 +
 hw/arm/mps2-tz.c |   23 +-
 hw/arm/mps2.c|   65 ++-
 hw/arm/realview.c|3 +-
 hw/arm/versatilepb.c |3 +-
 hw/arm/vexpress.c|3 +-
 hw/arm/virt.c|   63 +-
 hw/i2c/versatile_i2c.c   |   38 +-
 hw/watchdog/cmsdk-apb-watchdog.c |1 +
 target/arm/cpu.c |2 +-
 target/arm/cpu64.c   |   10 +-
 target/arm/kvm.c |4 +-
 target/arm/kvm64.c   |   14 +-
 target/arm/translate-a64.c   |   20 +-
 target/arm/translate-neon.inc.c  | 1191 +-
 target/arm/translate-vfp.inc.c   |7 +-
 target/arm/translate.c   | 1064 +-

Re: [PULL 00/42] target-arm queue

2019-10-25 Thread Peter Maydell

On Fri, 25 Oct 2019 at 13:12, Peter Maydell  wrote:
>
> Changes from v1: dropped SVE patchset.
>
> The following changes since commit 58560ad254fbda71d4daa6622d71683190070ee2:
>
>   Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.2-20191024' 
> into staging (2019-10-24 16:22:58 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20191025
>
> for you to fetch changes up to f9469c1a01c333c08980e083e0ad3417256c8b9c:
>
>   hw/arm/highbank: Use AddressSpace when using write_secondary_boot() 
> (2019-10-25 13:09:27 +0100)
>
> 
> target-arm queue:
>  * raspi boards: some cleanup
>  * raspi: implement the bcm2835 system timer device
>  * raspi: implement a dummy thermal sensor
>  * misc devices: switch to ptimer transaction API
>  * cache TB flag state to improve performance of cpu_get_tb_cpu_state
>  * aspeed: Add an AST2600 eval board


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/4.2
for any user-visible changes.

-- PMM

[PULL 00/42] target-arm queue

2019-10-25 Thread Peter Maydell

Changes from v1: dropped SVE patchset.

The following changes since commit 58560ad254fbda71d4daa6622d71683190070ee2:

  Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.2-20191024' into 
staging (2019-10-24 16:22:58 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20191025

for you to fetch changes up to f9469c1a01c333c08980e083e0ad3417256c8b9c:

  hw/arm/highbank: Use AddressSpace when using write_secondary_boot() 
(2019-10-25 13:09:27 +0100)


target-arm queue:
 * raspi boards: some cleanup
 * raspi: implement the bcm2835 system timer device
 * raspi: implement a dummy thermal sensor
 * misc devices: switch to ptimer transaction API
 * cache TB flag state to improve performance of cpu_get_tb_cpu_state
 * aspeed: Add an AST2600 eval board


Cédric Le Goater (2):
  hw/gpio: Fix property accessors of the AST2600 GPIO 1.8V model
  aspeed: Add an AST2600 eval board

Peter Maydell (8):
  hw/net/fsl_etsec/etsec.c: Switch to transaction-based ptimer API
  hw/timer/xilinx_timer.c: Switch to transaction-based ptimer API
  hw/dma/xilinx_axidma.c: Switch to transaction-based ptimer API
  hw/timer/slavio_timer: Remove useless check for NULL t->timer
  hw/timer/slavio_timer.c: Switch to transaction-based ptimer API
  hw/timer/grlib_gptimer.c: Switch to transaction-based ptimer API
  hw/m68k/mcf5206.c: Switch to transaction-based ptimer API
  hw/watchdog/milkymist-sysctl.c: Switch to transaction-based ptimer API

Philippe Mathieu-Daudé (8):
  hw/misc/bcm2835_thermal: Add a dummy BCM2835 thermal sensor
  hw/arm/bcm2835_peripherals: Use the thermal sensor block
  hw/timer/bcm2835: Add the BCM2835 SYS_timer
  hw/arm/bcm2835_peripherals: Use the SYS_timer
  hw/arm/bcm2836: Make the SoC code modular
  hw/arm/bcm2836: Rename cpus[] as cpu[].core
  hw/arm/raspi: Use AddressSpace when using arm_boot::write_secondary_boot
  hw/arm/highbank: Use AddressSpace when using write_secondary_boot()

Richard Henderson (24):
  target/arm: Split out rebuild_hflags_common
  target/arm: Split out rebuild_hflags_a64
  target/arm: Split out rebuild_hflags_common_32
  target/arm: Split arm_cpu_data_is_big_endian
  target/arm: Split out rebuild_hflags_m32
  target/arm: Reduce tests vs M-profile in cpu_get_tb_cpu_state
  target/arm: Split out rebuild_hflags_a32
  target/arm: Split out rebuild_hflags_aprofile
  target/arm: Hoist XSCALE_CPAR, VECLEN, VECSTRIDE in cpu_get_tb_cpu_state
  target/arm: Simplify set of PSTATE_SS in cpu_get_tb_cpu_state
  target/arm: Hoist computation of TBFLAG_A32.VFPEN
  target/arm: Add arm_rebuild_hflags
  target/arm: Split out arm_mmu_idx_el
  target/arm: Hoist store to cs_base in cpu_get_tb_cpu_state
  target/arm: Add HELPER(rebuild_hflags_{a32, a64, m32})
  target/arm: Rebuild hflags at EL changes
  target/arm: Rebuild hflags at MSR writes
  target/arm: Rebuild hflags at CPSR writes
  target/arm: Rebuild hflags at Xscale SCTLR writes
  target/arm: Rebuild hflags for M-profile
  target/arm: Rebuild hflags for M-profile NVIC
  linux-user/aarch64: Rebuild hflags for TARGET_WORDS_BIGENDIAN
  linux-user/arm: Rebuild hflags for TARGET_WORDS_BIGENDIAN
  target/arm: Rely on hflags correct in cpu_get_tb_cpu_state

 hw/misc/Makefile.objs|   1 +
 hw/timer/Makefile.objs   |   1 +
 hw/net/fsl_etsec/etsec.h |   1 -
 include/hw/arm/aspeed.h  |   1 +
 include/hw/arm/bcm2835_peripherals.h |   5 +-
 include/hw/arm/bcm2836.h |   4 +-
 include/hw/arm/raspi_platform.h  |   1 +
 include/hw/misc/bcm2835_thermal.h|  27 +++
 include/hw/timer/bcm2835_systmr.h|  33 +++
 target/arm/cpu.h |  84 +---
 target/arm/helper.h  |   4 +
 target/arm/internals.h   |   9 +
 hw/arm/aspeed.c  |  23 ++
 hw/arm/bcm2835_peripherals.c |  30 ++-
 hw/arm/bcm2836.c |  44 ++--
 hw/arm/highbank.c|   3 +-
 hw/arm/raspi.c   |  14 +-
 hw/dma/xilinx_axidma.c   |   9 +-
 hw/gpio/aspeed_gpio.c|   8 +-
 hw/intc/armv7m_nvic.c|  22 +-
 hw/m68k/mcf5206.c|  15 +-
 hw/misc/bcm2835_thermal.c| 135 
 hw/net/fsl_etsec/etsec.c |   9 +-
 hw/timer/bcm2835_systmr.c| 163 +++
 hw/timer/grlib_gptimer.c |  28 ++-
 hw/timer/milkymist-sysctl.c  |  25 ++-
 hw/timer/slavio_timer.c  |  32 ++-
 hw/timer/xilinx_timer.c  |  13 +-
 linux-user/aarch64/cpu_loop.c|   1 +
 linux-user/arm/cpu_loop.c|   1 +
 linux-user/syscall.c

Re: [Qemu-devel] [PULL 00/42] target-arm queue

2019-04-29 Thread Peter Maydell

On Mon, 29 Apr 2019 at 18:00, Peter Maydell  wrote:
>
> First pullreq for arm of the 4.1 series, since I'm back from
> holiday now. This is mostly my M-profile FPU series and Philippe's
> devices.h cleanup. I have a pile of other patchsets to work through
> in my to-review folder, but 42 patches is definitely quite
> big enough to send now...
>
> thanks
> -- PMM
>
> The following changes since commit 413a99a92c13ec408dcf2adaa87918dc81e890c8:
>
>   Add Nios II semihosting support. (2019-04-29 16:09:51 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20190429
>
> for you to fetch changes up to 437cc27ddfded3bbab6afd5ac1761e0e195edba7:
>
>   hw/devices: Move SMSC 91C111 declaration into a new header (2019-04-29 
> 17:57:21 +0100)
>
> 
> target-arm queue:
>  * remove "bag of random stuff" hw/devices.h header
>  * implement FPU for Cortex-M and enable it for Cortex-M4 and -M33
>  * hw/dma: Compile the bcm2835_dma device as common object
>  * configure: Remove --source-path option
>  * hw/ssi/xilinx_spips: Avoid variable length array
>  * hw/arm/smmuv3: Remove SMMUNotifierNode
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/4.1
for any user-visible changes.

-- PMM

[Qemu-devel] [PULL 00/42] target-arm queue

2019-04-29 Thread Peter Maydell

First pullreq for arm of the 4.1 series, since I'm back from
holiday now. This is mostly my M-profile FPU series and Philippe's
devices.h cleanup. I have a pile of other patchsets to work through
in my to-review folder, but 42 patches is definitely quite
big enough to send now...

thanks
-- PMM

The following changes since commit 413a99a92c13ec408dcf2adaa87918dc81e890c8:

  Add Nios II semihosting support. (2019-04-29 16:09:51 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20190429

for you to fetch changes up to 437cc27ddfded3bbab6afd5ac1761e0e195edba7:

  hw/devices: Move SMSC 91C111 declaration into a new header (2019-04-29 
17:57:21 +0100)


target-arm queue:
 * remove "bag of random stuff" hw/devices.h header
 * implement FPU for Cortex-M and enable it for Cortex-M4 and -M33
 * hw/dma: Compile the bcm2835_dma device as common object
 * configure: Remove --source-path option
 * hw/ssi/xilinx_spips: Avoid variable length array
 * hw/arm/smmuv3: Remove SMMUNotifierNode


Eric Auger (1):
  hw/arm/smmuv3: Remove SMMUNotifierNode

Peter Maydell (28):
  hw/ssi/xilinx_spips: Avoid variable length array
  configure: Remove --source-path option
  target/arm: Make sure M-profile FPSCR RES0 bits are not settable
  hw/intc/armv7m_nvic: Allow reading of M-profile MVFR* registers
  target/arm: Implement dummy versions of M-profile FP-related registers
  target/arm: Disable most VFP sysregs for M-profile
  target/arm: Honour M-profile FP enable bits
  target/arm: Decode FP instructions for M profile
  target/arm: Clear CONTROL_S.SFPA in SG insn if FPU present
  target/arm: Handle SFPA and FPCA bits in reads and writes of CONTROL
  target/arm/helper: don't return early for STKOF faults during stacking
  target/arm: Handle floating point registers in exception entry
  target/arm: Implement v7m_update_fpccr()
  target/arm: Clear CONTROL.SFPA in BXNS and BLXNS
  target/arm: Clean excReturn bits when tail chaining
  target/arm: Allow for floating point in callee stack integrity check
  target/arm: Handle floating point registers in exception return
  target/arm: Move NS TBFLAG from bit 19 to bit 6
  target/arm: Overlap VECSTRIDE and XSCALE_CPAR TB flags
  target/arm: Set FPCCR.S when executing M-profile floating point insns
  target/arm: Activate M-profile floating point context when FPCCR.ASPEN is 
set
  target/arm: New helper function arm_v7m_mmu_idx_all()
  target/arm: New function armv7m_nvic_set_pending_lazyfp()
  target/arm: Add lazy-FP-stacking support to v7m_stack_write()
  target/arm: Implement M-profile lazy FP state preservation
  target/arm: Implement VLSTM for v7M CPUs with an FPU
  target/arm: Implement VLLDM for v7M CPUs with an FPU
  target/arm: Enable FPU for Cortex-M4 and Cortex-M33

Philippe Mathieu-Daudé (13):
  hw/dma: Compile the bcm2835_dma device as common object
  hw/arm/aspeed: Use TYPE_TMP105/TYPE_PCA9552 instead of hardcoded string
  hw/arm/nseries: Use TYPE_TMP105 instead of hardcoded string
  hw/display/tc6393xb: Remove unused functions
  hw/devices: Move TC6393XB declarations into a new header
  hw/devices: Move Blizzard declarations into a new header
  hw/devices: Move CBus declarations into a new header
  hw/devices: Move Gamepad declarations into a new header
  hw/devices: Move TI touchscreen declarations into a new header
  hw/devices: Move LAN9118 declarations into a new header
  hw/net/ne2000-isa: Add guards to the header
  hw/net/lan9118: Export TYPE_LAN9118 and use it instead of hardcoded string
  hw/devices: Move SMSC 91C111 declaration into a new header

 configure |  10 +-
 hw/dma/Makefile.objs  |   2 +-
 include/hw/arm/omap.h |   6 +-
 include/hw/arm/smmu-common.h  |   8 +-
 include/hw/devices.h  |  62 ---
 include/hw/display/blizzard.h |  22 ++
 include/hw/display/tc6393xb.h |  24 ++
 include/hw/input/gamepad.h|  19 +
 include/hw/input/tsc2xxx.h|  36 ++
 include/hw/misc/cbus.h|  32 ++
 include/hw/net/lan9118.h  |  21 +
 include/hw/net/ne2000-isa.h   |   6 +
 include/hw/net/smc91c111.h|  19 +
 include/qemu/typedefs.h   |   1 -
 target/arm/cpu.h  |  95 -
 target/arm/helper.h   |   5 +
 target/arm/translate.h|   3 +
 hw/arm/aspeed.c   |  13 +-
 hw/arm/exynos4_boards.c   |   3 +-
 hw/arm/gumstix.c  |   2 +-
 hw/arm/integratorcp.c |   2 +-
 hw/arm/kzm.c  |   2 +-
 hw/arm/mainstone.c|   2 +-
 hw/arm/mps2-tz.c  |   3 +-
 hw/arm/mps2.c |   2 +-
 hw/arm/nseries.c  |   7 +-
 hw/arm/palm.c |   2 +-

Re: [Qemu-devel] [PULL 00/42] target-arm queue

2018-03-01 Thread Fam Zheng

On Thu, Mar 1, 2018 at 10:45 PM, Peter Maydell <peter.mayd...@linaro.org> wrote:
> On 1 March 2018 at 13:00,  <no-re...@patchew.org> wrote:
>> Hi,
>>
>> This series seems to have some coding style problems. See output below for
>> more information:
>>
>> Type: series
>> Message-id: 20180301112403.12487-1-peter.mayd...@linaro.org
>> Subject: [Qemu-devel] [PULL 00/42] target-arm queue
>
> Fam -- any idea why patchew sent two checkpatch-issues emails for
> this patchset ? The Message-IDs are:
> <151990924540.1290.18181910407458585370@bdbb90650ae5>
> <151990926291.1290.9842237231347453757@bdbb90650ae5>

A bug in patchew. The server dispatched the checkpatch task to two testers
when they asked for more work to do. One of them shouldn't happen.
I've worked around this in the config
(filtering the task into only one tester) now.

I created an issue.

https://github.com/patchew-project/patchew/issues/63

Fam

Re: [Qemu-devel] [PULL 00/42] target-arm queue

2018-03-01 Thread Peter Maydell

On 1 March 2018 at 11:23, Peter Maydell  wrote:
> Arm queue -- I have more stuff pending but I prefer to push
> this first lot out and keep the pull below 50 patches.
> Most of this is Alex's FP16 support work.
>
> -- PMM
>
>
> The following changes since commit 6697439794f72b3501ee16bb95d16854f9981421:
>
>   Merge remote-tracking branch 
> 'remotes/kraxel/tags/usb-20180227-pull-request' into staging (2018-02-27 
> 17:50:46 +)
>
> are available in the Git repository at:
>
>   git://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20180301
>
> for you to fetch changes up to c22e580c2ad1cccef582e1490e732f254d4ac064:
>
>   MAINTAINERS: Update my email address (2018-03-01 11:13:59 +)
>
> 
> target-arm queue:
>  * update MAINTAINERS for Alistair's new email address
>  * add Arm v8.2 FP16 arithmetic extension for linux-user
>  * implement display connector emulation for vexpress board
>  * xilinx_spips: Enable only two slaves when reading/writing with stripe
>  * xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
>  * hw: register: Run post_write hook on reset
>
> 

Applied, thanks.

-- PMM

Re: [Qemu-devel] [PULL 00/42] target-arm queue

2018-03-01 Thread Peter Maydell

On 1 March 2018 at 13:00,  <no-re...@patchew.org> wrote:
> Hi,
>
> This series seems to have some coding style problems. See output below for
> more information:
>
> Type: series
> Message-id: 20180301112403.12487-1-peter.mayd...@linaro.org
> Subject: [Qemu-devel] [PULL 00/42] target-arm queue

Fam -- any idea why patchew sent two checkpatch-issues emails for
this patchset ? The Message-IDs are:
<151990924540.1290.18181910407458585370@bdbb90650ae5>
<151990926291.1290.9842237231347453757@bdbb90650ae5>

thanks
-- PMM

Re: [Qemu-devel] [PULL 00/42] target-arm queue

2018-03-01 Thread no-reply

Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20180301112403.12487-1-peter.mayd...@linaro.org
Subject: [Qemu-devel] [PULL 00/42] target-arm queue

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
   5116c331c6..2963d78204  master -> master
 * [new tag]   
patchew/20180301112403.12487-1-peter.mayd...@linaro.org -> 
patchew/20180301112403.12487-1-peter.mayd...@linaro.org
Switched to a new branch 'test'
b8d820da8e MAINTAINERS: Update my email address
fafefeede8 linux-user: Report AArch64 FP16 support via hwcap bits
1e47f0c8d0 target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU
a1d78601d3 arm/translate-a64: add all single op FP16 to handle_fp_1src_half
ef1aeecd4b arm/translate-a64: implement simd_scalar_three_reg_same_fp16
6f2836d485 arm/translate-a64: add all FP16 ops in simd_scalar_pairwise
a35291f349 arm/translate-a64: add FP16 FMOV to simd_mod_imm
0a27cbb4ed arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
0a441b7da4 arm/helper.c: re-factor rsqrte and add rsqrte_f16
da2e0fc44a arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
4cef2369d2 arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
1b4f1ab980 arm/translate-a64: add FP16 FRECPE
73a9e97036 arm/helper.c: re-factor recpe and add recepe_f16
90ba4bd8c2 arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
73fd85ed2b arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
f19cc5a183 arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
65f396e589 arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
0e24214ab5 arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
f196ce6fe6 arm/translate-a64: initial decode for simd_two_reg_misc_fp16
34d06595e7 arm/translate-a64: add FP16 x2 ops for simd_indexed
1cbb0530d6 arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed
2784d82ed6 arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16
d384cdd281 arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
8f8a6ce448 arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
126916bc89 arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to 
simd_three_reg_same_fp16
4173362d9a arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to 
simd_three_reg_same_fp16
933cd48012 arm/translate-a64: initial decode for simd_three_reg_same_fp16
b990db46a4 arm/translate-a64: handle_3same_64 comment fix
d35bfc6ddd arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
f7b5043d8e target/arm/helper: pass explicit fpst to set_rmode
f4942cc7c8 target/arm/cpu.h: add additional float_status flags
8f2a0f5575 target/arm/cpu.h: update comment for half-precision values
3059f5906d target/arm/cpu64: introduce ARM_V8_FP16 feature bit
aac25f27be include/exec/helper-head.h: support f16 in helper calls
5998ce1e24 arm/vexpress: Add proper display connector emulation
cd734131b2 hw/sii9022: Add support for Silicon Image SII9022
94b945c24d hw/i2c-ddc: Do not fail writes
fb66477d35 i2c: Move the bus class to i2c.h
96b6d99806 i2c: Fix some brace style issues
6fdd76003e xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
0a63d14eaa xilinx_spips: Enable only two slaves when reading/writing with stripe
3a5412277e hw: register: Run post_write hook on reset

=== OUTPUT BEGIN ===
Checking PATCH 1/42: hw: register: Run post_write hook on reset...
Checking PATCH 2/42: xilinx_spips: Enable only two slaves when reading/writing 
with stripe...
Checking PATCH 3/42: xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 
commands...
Checking PATCH 4/42: i2c: Fix some brace style issues...
Checking PATCH 5/42: i2c: Move the bus class to i2c.h...
Checking PATCH 6/42: hw/i2c-ddc: Do not fail writes...
Checking PATCH 7/42: hw/sii9022: Add support for Silicon Image SII9022...
Checking PATCH 8/42: arm/vexpress: Add proper display connector emulation...
Checking PATCH 9/42: include/exec/helper-head.h: support f16 in helper calls...
Checking PATCH 10/42: target/arm/cpu64: introduce ARM_V8_FP16 feature bit...
Checking PATCH 11/42: target/arm/cpu.h: update comment for half-precision 
values...
Checking PATCH 12/42: target/arm/cpu.h: add additional float_status flags...
Checking PATCH 13/42: target/arm/helper: pass explicit fpst to set_rmode...
Checking PATCH 14/42: arm/translate-a64: implem

Re: [Qemu-devel] [PULL 00/42] target-arm queue

2018-03-01 Thread no-reply

Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20180301112403.12487-1-peter.mayd...@linaro.org
Subject: [Qemu-devel] [PULL 00/42] target-arm queue

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
   5116c331c6..2963d78204  master -> master
 * [new tag]   
patchew/20180301112403.12487-1-peter.mayd...@linaro.org -> 
patchew/20180301112403.12487-1-peter.mayd...@linaro.org
Switched to a new branch 'test'
b8d820da8e MAINTAINERS: Update my email address
fafefeede8 linux-user: Report AArch64 FP16 support via hwcap bits
1e47f0c8d0 target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU
a1d78601d3 arm/translate-a64: add all single op FP16 to handle_fp_1src_half
ef1aeecd4b arm/translate-a64: implement simd_scalar_three_reg_same_fp16
6f2836d485 arm/translate-a64: add all FP16 ops in simd_scalar_pairwise
a35291f349 arm/translate-a64: add FP16 FMOV to simd_mod_imm
0a27cbb4ed arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
0a441b7da4 arm/helper.c: re-factor rsqrte and add rsqrte_f16
da2e0fc44a arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
4cef2369d2 arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
1b4f1ab980 arm/translate-a64: add FP16 FRECPE
73a9e97036 arm/helper.c: re-factor recpe and add recepe_f16
90ba4bd8c2 arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
73fd85ed2b arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
f19cc5a183 arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
65f396e589 arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
0e24214ab5 arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
f196ce6fe6 arm/translate-a64: initial decode for simd_two_reg_misc_fp16
34d06595e7 arm/translate-a64: add FP16 x2 ops for simd_indexed
1cbb0530d6 arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed
2784d82ed6 arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16
d384cdd281 arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
8f8a6ce448 arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
126916bc89 arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to 
simd_three_reg_same_fp16
4173362d9a arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to 
simd_three_reg_same_fp16
933cd48012 arm/translate-a64: initial decode for simd_three_reg_same_fp16
b990db46a4 arm/translate-a64: handle_3same_64 comment fix
d35bfc6ddd arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
f7b5043d8e target/arm/helper: pass explicit fpst to set_rmode
f4942cc7c8 target/arm/cpu.h: add additional float_status flags
8f2a0f5575 target/arm/cpu.h: update comment for half-precision values
3059f5906d target/arm/cpu64: introduce ARM_V8_FP16 feature bit
aac25f27be include/exec/helper-head.h: support f16 in helper calls
5998ce1e24 arm/vexpress: Add proper display connector emulation
cd734131b2 hw/sii9022: Add support for Silicon Image SII9022
94b945c24d hw/i2c-ddc: Do not fail writes
fb66477d35 i2c: Move the bus class to i2c.h
96b6d99806 i2c: Fix some brace style issues
6fdd76003e xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
0a63d14eaa xilinx_spips: Enable only two slaves when reading/writing with stripe
3a5412277e hw: register: Run post_write hook on reset

=== OUTPUT BEGIN ===
Checking PATCH 1/42: hw: register: Run post_write hook on reset...
Checking PATCH 2/42: xilinx_spips: Enable only two slaves when reading/writing 
with stripe...
Checking PATCH 3/42: xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 
commands...
Checking PATCH 4/42: i2c: Fix some brace style issues...
Checking PATCH 5/42: i2c: Move the bus class to i2c.h...
Checking PATCH 6/42: hw/i2c-ddc: Do not fail writes...
Checking PATCH 7/42: hw/sii9022: Add support for Silicon Image SII9022...
Checking PATCH 8/42: arm/vexpress: Add proper display connector emulation...
Checking PATCH 9/42: include/exec/helper-head.h: support f16 in helper calls...
Checking PATCH 10/42: target/arm/cpu64: introduce ARM_V8_FP16 feature bit...
Checking PATCH 11/42: target/arm/cpu.h: update comment for half-precision 
values...
Checking PATCH 12/42: target/arm/cpu.h: add additional float_status flags...
Checking PATCH 13/42: target/arm/helper: pass explicit fpst to set_rmode...
Checking PATCH 14/42: arm/translate-a64: implem

[Qemu-devel] [PULL 00/42] target-arm queue

2018-03-01 Thread Peter Maydell

Arm queue -- I have more stuff pending but I prefer to push
this first lot out and keep the pull below 50 patches.
Most of this is Alex's FP16 support work.

-- PMM


The following changes since commit 6697439794f72b3501ee16bb95d16854f9981421:

  Merge remote-tracking branch 'remotes/kraxel/tags/usb-20180227-pull-request' 
into staging (2018-02-27 17:50:46 +)

are available in the Git repository at:

  git://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20180301

for you to fetch changes up to c22e580c2ad1cccef582e1490e732f254d4ac064:

  MAINTAINERS: Update my email address (2018-03-01 11:13:59 +)


target-arm queue:
 * update MAINTAINERS for Alistair's new email address
 * add Arm v8.2 FP16 arithmetic extension for linux-user
 * implement display connector emulation for vexpress board
 * xilinx_spips: Enable only two slaves when reading/writing with stripe
 * xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands
 * hw: register: Run post_write hook on reset


Alex Bennée (31):
  include/exec/helper-head.h: support f16 in helper calls
  target/arm/cpu64: introduce ARM_V8_FP16 feature bit
  target/arm/cpu.h: update comment for half-precision values
  target/arm/cpu.h: add additional float_status flags
  target/arm/helper: pass explicit fpst to set_rmode
  arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
  arm/translate-a64: handle_3same_64 comment fix
  arm/translate-a64: initial decode for simd_three_reg_same_fp16
  arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to 
simd_three_reg_same_fp16
  arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16
  arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
  arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
  arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16
  arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed
  arm/translate-a64: add FP16 x2 ops for simd_indexed
  arm/translate-a64: initial decode for simd_two_reg_misc_fp16
  arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
  arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
  arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
  arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
  arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
  arm/helper.c: re-factor recpe and add recepe_f16
  arm/translate-a64: add FP16 FRECPE
  arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
  arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
  arm/helper.c: re-factor rsqrte and add rsqrte_f16
  arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
  arm/translate-a64: add FP16 FMOV to simd_mod_imm
  arm/translate-a64: add all FP16 ops in simd_scalar_pairwise
  arm/translate-a64: implement simd_scalar_three_reg_same_fp16
  arm/translate-a64: add all single op FP16 to handle_fp_1src_half

Alistair Francis (2):
  hw: register: Run post_write hook on reset
  MAINTAINERS: Update my email address

Corey Minyard (2):
  i2c: Fix some brace style issues
  i2c: Move the bus class to i2c.h

Francisco Iglesias (2):
  xilinx_spips: Enable only two slaves when reading/writing with stripe
  xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands

Linus Walleij (3):
  hw/i2c-ddc: Do not fail writes
  hw/sii9022: Add support for Silicon Image SII9022
  arm/vexpress: Add proper display connector emulation

Peter Maydell (2):
  target/arm: Enable ARM_V8_FP16 feature bit for the AArch64 "any" CPU
  linux-user: Report AArch64 FP16 support via hwcap bits

 hw/display/Makefile.objs|1 +
 include/exec/helper-head.h  |3 +
 include/fpu/softfloat.h |   18 +-
 include/hw/i2c/i2c.h|   23 +-
 include/hw/register.h   |6 +-
 target/arm/cpu.h|   34 +-
 target/arm/helper-a64.h |   33 +
 target/arm/helper.h |   14 +-
 hw/arm/vexpress.c   |6 +-
 hw/core/register.c  |8 +
 hw/display/sii9022.c|  191 ++
 hw/i2c/core.c   |   18 -
 hw/i2c/i2c-ddc.c|4 +-
 hw/ssi/xilinx_spips.c   |   43 +-
 linux-user/elfload.c|2 +
 target/arm/cpu64.c  |1 +
 target/arm/helper-a64.c |  269 +
 target/arm/helper.c |  481 ---
 target/arm/translate-a64.c  | 1266 +--
 target/arm/translate.c  |   12 +-
 MAINTAINERS |   12 +-
 default-configs/arm-softmmu.mak |2 +
 hw/display/trace-events |5 +
 23 files changed, 1981 insertions(+), 471 deletions(-)
 create

Re: [PULL 00/42] target-arm queue

[PULL 00/42] target-arm queue

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Re: [PULL 00/42] target-arm queue

[PULL 00/42] target-arm queue

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[PULL 00/42] target-arm queue

Re: [Qemu-devel] [PULL 00/42] target-arm queue

[Qemu-devel] [PULL 00/42] target-arm queue

Re: [Qemu-devel] [PULL 00/42] target-arm queue

Re: [Qemu-devel] [PULL 00/42] target-arm queue

Re: [Qemu-devel] [PULL 00/42] target-arm queue

Re: [Qemu-devel] [PULL 00/42] target-arm queue

Re: [Qemu-devel] [PULL 00/42] target-arm queue

[Qemu-devel] [PULL 00/42] target-arm queue

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