Re: [PULL 00/47] target-arm queue

2020-09-02 Thread no-reply 
Patchew URL: 
https://patchew.org/QEMU/20200901151823.29785-1-peter.mayd...@linaro.org/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20200901151823.29785-1-peter.mayd...@linaro.org
Subject: [PULL 00/47] target-arm queue

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag] 
patchew/159903454714.28509.7439453309116734374.stgit@pasha-ThinkPad-X280 -> 
patchew/159903454714.28509.7439453309116734374.stgit@pasha-ThinkPad-X280
 - [tag update]  patchew/20200828104102.4490-1-ahmedkhaledkara...@gmail.com 
-> patchew/20200828104102.4490-1-ahmedkhaledkara...@gmail.com
 - [tag update]  patchew/20200901101951.85892-1-f4...@amsat.org -> 
patchew/20200901101951.85892-1-f4...@amsat.org
 - [tag update]  patchew/20200901143424.884735-1-mre...@redhat.com -> 
patchew/20200901143424.884735-1-mre...@redhat.com
 - [tag update]  patchew/20200902080552.159806-1-phi...@redhat.com -> 
patchew/20200902080552.159806-1-phi...@redhat.com
 * [new tag] patchew/20200902080801.160652-1-phi...@redhat.com -> 
patchew/20200902080801.160652-1-phi...@redhat.com
 * [new tag] patchew/20200902080909.161034-1-phi...@redhat.com -> 
patchew/20200902080909.161034-1-phi...@redhat.com
 * [new tag] patchew/20200902081445.3291-1-kra...@redhat.com -> 
patchew/20200902081445.3291-1-kra...@redhat.com
Switched to a new branch 'test'
867f12e hw/arm/sbsa-ref : Add embedded controller in secure memory
ef9b9cb hw/misc/sbsa_ec : Add an embedded controller for sbsa-ref
845f48a hw/arm/sbsa-ref: add "reg" property to DT cpu nodes
3cac290 target/arm: Enable FP16 in '-cpu max'
7ac1305 target/arm: Implement fp16 for Neon VMUL, VMLA, VMLS
8e7d9e3 target/arm/vec_helper: Add gvec fp indexed multiply-and-add operations
2fb3424 target/arm/vec_helper: Handle oprsz less than 16 bytes in indexed 
operations
db719f9 target/arm: Implement fp16 for Neon VRINTX
07d6f02 target/arm: Implement fp16 for Neon VRINT-with-specified-rounding-mode
0480984 target/arm: Implement fp16 for Neon VCVT with rounding modes
6fa11fb target/arm: Implement fp16 for Neon VCVT fixed-point
9a7522a target/arm: Convert Neon VCVT fixed-point to gvec
dff0402 target/arm: Implement fp16 for Neon float-integer VCVT
78bda89 target/arm: Implement fp16 for Neon pairwise fp ops
7cc318e target/arm: Implement fp16 for Neon VRSQRTS
5662f40 target/arm: Implement fp16 for Neon VRECPS
943b926 target/arm: Implement fp16 for Neon fp compare-vs-0
3a0d121 target/arm: Implement fp16 for Neon VFMA, VMFS
ff5b42c target/arm: Implement fp16 for Neon VMLA, VMLS operations
a6112ba target/arm: Implement fp16 for Neon VMAXNM, VMINNM
d2e6add target/arm: Implement fp16 for Neon VMAX, VMIN
db83f64 target/arm: Implement fp16 for VACGE, VACGT
ae8a9f3 target/arm: Implement fp16 for VCEQ, VCGE, VCGT comparisons
6383a67 target/arm: Implement fp16 for Neon VABS, VNEG of floats
aa9fecc target/arm: Implement fp16 for Neon VRECPE, VRSQRTE using gvec
ccc9e6e target/arm: Implement FP16 for Neon VADD, VSUB, VABD, VMUL
fe782c1 target/arm: Implement VFP fp16 VMOV between gp and halfprec registers
77ca57c target/arm: Implement new VFP fp16 insn VMOVX
92aba48 target/arm: Implement new VFP fp16 insn VINS
ee2de45 target/arm: Implement VFP fp16 VRINT*
3c18e85 target/arm: Implement VFP fp16 VSEL
06590c3 target/arm: Implement VFP vp16 VCVT-with-specified-rounding-mode
bc421d5 target/arm: Implement VFP fp16 VCVT between float and fixed-point
ad1cb81 target/arm: Use macros instead of open-coding fp16 conversion helpers
93f7d9e target/arm: Make VFP_CONV_FIX macros take separate float type and float 
size
9c34df8 target/arm: Implement VFP fp16 VCVT between float and integer
32431b7 target/arm: Implement VFP fp16 VLDR and VSTR
9e7ad8d target/arm: Implement VFP fp16 VCMP
219e5e7 target/arm: Implement VFP fp16 for VMOV immediate
16625ab target/arm: Implement VFP fp16 for VABS, VNEG, VSQRT
af78af0 target/arm: Macroify uses of do_vfp_2op_sp() and do_vfp_2op_dp()
790c683 target/arm: Implement VFP fp16 for fused-multiply-add
03011ed target/arm: Macroify trans functions for VFMA, VFMS, VFNMA, VFNMS
9e8666f target/arm: Implement VFP fp16 VMLA, VMLS, VNMLS, VNMLA, VNMUL
dc07ef0 target/arm: Implement VFP fp16 for VFP_BINOP operations
eac3fc0 target/arm: Use correct ID register check for aa32_fp16_arith
348acc9 target/arm: Remove local definitions of float constants

=== OUTPUT BEGIN ===
1/47 Checking commit 348acc9c588e (target/arm: Remove local definitions of 
float constants)
2/47 Checking commit eac3fc0b8d32 (target/arm: Use correct ID register check 
for aa32_fp16_arith)
3/47 Checking commi

Re: [PULL 00/47] target-arm queue

2020-09-01 Thread Peter Maydell 
On Tue, 1 Sep 2020 at 16:18, Peter Maydell  wrote:
>
> Just my fp16 work, plus some small stuff for the sbsa-ref board;
> but my rule of thumb is to send a pullreq once I get over about
> 30 patches...
>
> -- PMM
>
> The following changes since commit 2f4c51c0f384d7888a04b4815861e6d5fd244d75:
>
>   Merge remote-tracking branch 
> 'remotes/kraxel/tags/usb-20200831-pull-request' into staging (2020-08-31 
> 19:39:13 +0100)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20200901
>
> for you to fetch changes up to 3f462bf0f6ea6382dd1502d4eb1fcd33c8e774f5:
>
>   hw/arm/sbsa-ref : Add embedded controller in secure memory (2020-09-01 
> 14:01:34 +0100)
>
> 
> target-arm queue:
>  * Implement fp16 support for AArch32 VFP and Neon
>  * hw/arm/sbsa-ref: add "reg" property to DT cpu nodes
>  * hw/arm/sbsa-ref : Add embedded controller in secure memory
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/5.2
for any user-visible changes.

-- PMM

[PULL 00/47] target-arm queue

2020-09-01 Thread Peter Maydell 
Just my fp16 work, plus some small stuff for the sbsa-ref board;
but my rule of thumb is to send a pullreq once I get over about
30 patches...

-- PMM

The following changes since commit 2f4c51c0f384d7888a04b4815861e6d5fd244d75:

  Merge remote-tracking branch 'remotes/kraxel/tags/usb-20200831-pull-request' 
into staging (2020-08-31 19:39:13 +0100)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20200901

for you to fetch changes up to 3f462bf0f6ea6382dd1502d4eb1fcd33c8e774f5:

  hw/arm/sbsa-ref : Add embedded controller in secure memory (2020-09-01 
14:01:34 +0100)


target-arm queue:
 * Implement fp16 support for AArch32 VFP and Neon
 * hw/arm/sbsa-ref: add "reg" property to DT cpu nodes
 * hw/arm/sbsa-ref : Add embedded controller in secure memory


Graeme Gregory (2):
  hw/misc/sbsa_ec : Add an embedded controller for sbsa-ref
  hw/arm/sbsa-ref : Add embedded controller in secure memory

Leif Lindholm (1):
  hw/arm/sbsa-ref: add "reg" property to DT cpu nodes

Peter Maydell (44):
  target/arm: Remove local definitions of float constants
  target/arm: Use correct ID register check for aa32_fp16_arith
  target/arm: Implement VFP fp16 for VFP_BINOP operations
  target/arm: Implement VFP fp16 VMLA, VMLS, VNMLS, VNMLA, VNMUL
  target/arm: Macroify trans functions for VFMA, VFMS, VFNMA, VFNMS
  target/arm: Implement VFP fp16 for fused-multiply-add
  target/arm: Macroify uses of do_vfp_2op_sp() and do_vfp_2op_dp()
  target/arm: Implement VFP fp16 for VABS, VNEG, VSQRT
  target/arm: Implement VFP fp16 for VMOV immediate
  target/arm: Implement VFP fp16 VCMP
  target/arm: Implement VFP fp16 VLDR and VSTR
  target/arm: Implement VFP fp16 VCVT between float and integer
  target/arm: Make VFP_CONV_FIX macros take separate float type and float 
size
  target/arm: Use macros instead of open-coding fp16 conversion helpers
  target/arm: Implement VFP fp16 VCVT between float and fixed-point
  target/arm: Implement VFP vp16 VCVT-with-specified-rounding-mode
  target/arm: Implement VFP fp16 VSEL
  target/arm: Implement VFP fp16 VRINT*
  target/arm: Implement new VFP fp16 insn VINS
  target/arm: Implement new VFP fp16 insn VMOVX
  target/arm: Implement VFP fp16 VMOV between gp and halfprec registers
  target/arm: Implement FP16 for Neon VADD, VSUB, VABD, VMUL
  target/arm: Implement fp16 for Neon VRECPE, VRSQRTE using gvec
  target/arm: Implement fp16 for Neon VABS, VNEG of floats
  target/arm: Implement fp16 for VCEQ, VCGE, VCGT comparisons
  target/arm: Implement fp16 for VACGE, VACGT
  target/arm: Implement fp16 for Neon VMAX, VMIN
  target/arm: Implement fp16 for Neon VMAXNM, VMINNM
  target/arm: Implement fp16 for Neon VMLA, VMLS operations
  target/arm: Implement fp16 for Neon VFMA, VMFS
  target/arm: Implement fp16 for Neon fp compare-vs-0
  target/arm: Implement fp16 for Neon VRECPS
  target/arm: Implement fp16 for Neon VRSQRTS
  target/arm: Implement fp16 for Neon pairwise fp ops
  target/arm: Implement fp16 for Neon float-integer VCVT
  target/arm: Convert Neon VCVT fixed-point to gvec
  target/arm: Implement fp16 for Neon VCVT fixed-point
  target/arm: Implement fp16 for Neon VCVT with rounding modes
  target/arm: Implement fp16 for Neon VRINT-with-specified-rounding-mode
  target/arm: Implement fp16 for Neon VRINTX
  target/arm/vec_helper: Handle oprsz less than 16 bytes in indexed 
operations
  target/arm/vec_helper: Add gvec fp indexed multiply-and-add operations
  target/arm: Implement fp16 for Neon VMUL, VMLA, VMLS
  target/arm: Enable FP16 in '-cpu max'

 target/arm/cpu.h|   7 +-
 target/arm/helper.h | 133 ++-
 target/arm/neon-dp.decode   |   8 +-
 target/arm/vfp-uncond.decode|  27 +-
 target/arm/vfp.decode   |  34 +-
 hw/arm/sbsa-ref.c   |  43 ++-
 hw/misc/sbsa_ec.c   |  98 +
 target/arm/cpu.c|   3 +-
 target/arm/cpu64.c  |  10 +-
 target/arm/helper-a64.c |  11 -
 target/arm/translate-sve.c  |   4 -
 target/arm/vec_helper.c | 431 -
 target/arm/vfp_helper.c | 244 +---
 hw/misc/meson.build |   2 +
 target/arm/translate-neon.c.inc | 755 +
 target/arm/translate-vfp.c.inc  | 810 
 16 files changed, 1819 insertions(+), 801 deletions(-)
 create mode 100644 hw/misc/sbsa_ec.c

Re: [Qemu-devel] [PULL 00/47] target-arm queue

2019-02-03 Thread no-reply 
Patchew URL: 
https://patchew.org/QEMU/20190201160653.13829-1-peter.mayd...@linaro.org/



Hi,

This series failed the docker-mingw@fedora build test. Please find the testing 
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.

=== TEST SCRIPT BEGIN ===
#!/bin/bash
time make docker-test-mingw@fedora SHOW_ENV=1 J=14
=== TEST SCRIPT END ===


Configure options:
--enable-werror --target-list=x86_64-softmmu,aarch64-softmmu 
--prefix=/tmp/qemu-test/install --python=/usr/bin/python3 
--cross-prefix=x86_64-w64-mingw32- --enable-trace-backends=simple 
--enable-gnutls --enable-nettle --enable-curl --enable-vnc --enable-bzip2 
--enable-guest-agent --with-sdlabi=2.0
ERROR: unknown option --with-sdlabi=2.0
Try '/tmp/qemu-test/src/configure --help' for more information
# QEMU configure log Sun Feb  3 15:00:00 UTC 2019
# Configured with: '/tmp/qemu-test/src/configure' '--enable-werror' 
'--target-list=x86_64-softmmu,aarch64-softmmu' 
'--prefix=/tmp/qemu-test/install' '--python=/usr/bin/python3' 
'--cross-prefix=x86_64-w64-mingw32-' '--enable-trace-backends=simple' 
'--enable-gnutls' '--enable-nettle' '--enable-curl' '--enable-vnc' 
'--enable-bzip2' '--enable-guest-agent' '--with-sdlabi=2.0'
---
funcs: do_compiler do_cc compile_object check_define main
lines: 92 122 617 634 0
x86_64-w64-mingw32-gcc -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE 
-Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings 
-Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -std=gnu99 -c -o 
config-temp/qemu-conf.o config-temp/qemu-conf.c
config-temp/qemu-conf.c:2:2: error: #error __linux__ not defined
 #error __linux__ not defined
  ^

---
funcs: do_compiler do_cc compile_object check_define main
lines: 92 122 617 686 0
x86_64-w64-mingw32-gcc -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE 
-Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings 
-Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -std=gnu99 -c -o 
config-temp/qemu-conf.o config-temp/qemu-conf.c
config-temp/qemu-conf.c:2:2: error: #error __i386__ not defined
 #error __i386__ not defined
  ^

---
funcs: do_compiler do_cc compile_object check_define main
lines: 92 122 617 689 0
x86_64-w64-mingw32-gcc -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE 
-Wstrict-prototypes -Wredundant-decls -Wall -Wundef -Wwrite-strings 
-Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv -std=gnu99 -c -o 
config-temp/qemu-conf.o config-temp/qemu-conf.c
config-temp/qemu-conf.c:2:2: error: #error __ILP32__ not defined
 #error __ILP32__ not defined
  ^

---
lines: 92 128 920 0
x86_64-w64-mingw32-gcc -mthreads -D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 
-D_LARGEFILE_SOURCE -Wstrict-prototypes -Wredundant-decls -Wall -Wundef 
-Wwrite-strings -Wmissing-prototypes -fno-strict-aliasing -fno-common -fwrapv 
-std=gnu99 -o config-temp/qemu-conf.exe config-temp/qemu-conf.c -g -liberty
/usr/lib/gcc/x86_64-w64-mingw32/8.2.0/../../../../x86_64-w64-mingw32/bin/ld: 
cannot find -liberty
collect2: error: ld returned 1 exit status
Failed to run 'configure'
Traceback (most recent call last):
  File "./tests/docker/docker.py", line 563, in 


The full log is available at
http://patchew.org/logs/20190201160653.13829-1-peter.mayd...@linaro.org/testing.docker-mingw@fedora/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-de...@redhat.com

Re: [Qemu-devel] [PULL 00/47] target-arm queue

2019-02-01 Thread Peter Maydell 
On Fri, 1 Feb 2019 at 16:06, Peter Maydell  wrote:
>
> As promised, more Arm patches. The big thing in here is the
> MPS2-AN521 board model.
>
> thanks
> -- PMM
>
> The following changes since commit cfe6c547690b06fbce54a6d0f7b05dd7f18e36ea:
>
>   Merge remote-tracking branch 'remotes/xanclic/tags/pull-block-2019-01-31' 
> into staging (2019-01-31 19:26:09 +)
>
> are available in the Git repository at:
>
>   https://git.linaro.org/people/pmaydell/qemu-arm.git 
> tags/pull-target-arm-20190201
>
> for you to fetch changes up to 7743b70ffe7a8ce168adce2cf50ad156b1fefb8c:
>
>   tests/microbit-test: Add tests for nRF51 NVMC (2019-02-01 15:32:17 +)
>
> 
> target-arm queue:
>  * New machine mps2-an521 -- this is a model of the AN521 FPGA image for the 
> MPS2 devboard
>  * Fix various places where we failed to UNDEF invalid A64 instructions
>  * Don't UNDEF a valid FCMLA on 32-bit inputs
>  * Fix some bugs in the newly-added PAuth implementation
>  * microbit: Implement NVMC non-volatile memory controller
>

Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/4.0
for any user-visible changes.

-- PMM

[Qemu-devel] [PULL 00/47] target-arm queue

2019-02-01 Thread Peter Maydell 
As promised, more Arm patches. The big thing in here is the
MPS2-AN521 board model.

thanks
-- PMM

The following changes since commit cfe6c547690b06fbce54a6d0f7b05dd7f18e36ea:

  Merge remote-tracking branch 'remotes/xanclic/tags/pull-block-2019-01-31' 
into staging (2019-01-31 19:26:09 +)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git 
tags/pull-target-arm-20190201

for you to fetch changes up to 7743b70ffe7a8ce168adce2cf50ad156b1fefb8c:

  tests/microbit-test: Add tests for nRF51 NVMC (2019-02-01 15:32:17 +)


target-arm queue:
 * New machine mps2-an521 -- this is a model of the AN521 FPGA image for the 
MPS2 devboard
 * Fix various places where we failed to UNDEF invalid A64 instructions
 * Don't UNDEF a valid FCMLA on 32-bit inputs
 * Fix some bugs in the newly-added PAuth implementation
 * microbit: Implement NVMC non-volatile memory controller


Aaron Lindsay OS (2):
  target/arm: Send interrupts on PMU counter overflow
  target/arm: Add a timer to predict PMU counter overflow

Julia Suvorova (1):
  arm: Clarify the logic of set_pc()

Peter Maydell (33):
  armv7m: Don't assume the NVIC's CPU is CPU 0
  armv7m: Make cpu object a child of the armv7m container
  armv7m: Pass through start-powered-off CPU property
  hw/arm/iotkit: Rename IoTKit to ARMSSE
  hw/arm/iotkit: Refactor into abstract base class and subclass
  hw/arm/iotkit: Rename 'iotkit' local variables and functions
  hw/arm/iotkit: Rename files to hw/arm/armsse.[ch]
  hw/misc/iotkit-secctl: Support 4 internal MPCs
  hw/arm/armsse: Make number of SRAM banks parameterised
  hw/arm/armsse: Make SRAM bank size configurable
  hw/arm/armsse: Support dual-CPU configuration
  hw/arm/armsse: Give each CPU its own view of memory
  hw/arm/armsse: Put each CPU in its own cluster object
  iotkit-sysinfo: Make SYS_VERSION and SYS_CONFIG configurable
  hw/arm/armsse: Add unimplemented-device stubs for MHUs
  hw/arm/armsse: Add unimplemented-device stubs for PPUs
  hw/arm/armsse: Add unimplemented-device stub for cache control registers
  hw/arm/armsse: Add unimplemented-device stub for CPU local control 
registers
  hw/misc/armsse-cpuid: Implement SSE-200 CPU_IDENTITY register block
  hw/arm/armsse: Add CPU_IDENTITY block to SSE-200
  hw/arm/armsse: Add SSE-200 model
  hw/arm/mps2-tz: Add IRQ infrastructure to support SSE-200
  hw/arm/mps2-tz: Add mps2-an521 model
  target/arm/translate-a64: Don't underdecode system instructions
  target/arm/translate-a64: Don't underdecode PRFM
  target/arm/translate-a64: Don't underdecode SIMD ld/st multiple
  target/arm/translate-a64: Don't underdecode SIMD ld/st single
  target/arm/translate-a64: Don't underdecode add/sub extended register
  target/arm/translate-a64: Don't underdecode FP insns
  target/arm/translate-a64: Don't underdecode SDOT and UDOT
  exec.c: Don't reallocate IOMMUNotifiers that are in use
  target/arm/translate-a64: Fix FCMLA decoding error
  target/arm/translate-a64: Fix mishandling of size in FCMLA decode

Remi Denis-Courmont (2):
  target/arm: fix AArch64 virtual address space size
  target/arm: fix decoding of B{,L}RA{A,B}

Richard Henderson (5):
  target/arm: Enable API, APK bits in SCR, HCR
  target/arm: Always enable pac keys for user-only
  aarch64-linux-user: Update HWCAP bits from linux 5.0-rc1
  aarch64-linux-user: Enable HWCAP bits for PAuth
  linux-user: Initialize aarch64 pac keys

Steffen Görtz (3):
  hw/nvram/nrf51_nvm: Add nRF51 non-volatile memories
  arm: Instantiate NRF51 special NVM's and NVMC
  tests/microbit-test: Add tests for nRF51 NVMC

kumar sourav (1):
  hw/arm/nrf51_soc: set object owner in memory_region_init_ram

 hw/arm/Makefile.objs  |2 +-
 hw/misc/Makefile.objs |1 +
 hw/nvram/Makefile.objs|1 +
 include/hw/arm/{iotkit.h => armsse.h} |  113 ++-
 include/hw/arm/armv7m.h   |1 +
 include/hw/arm/nrf51_soc.h|2 +
 include/hw/misc/armsse-cpuid.h|   41 ++
 include/hw/misc/iotkit-secctl.h   |6 +-
 include/hw/misc/iotkit-sysinfo.h  |6 +
 include/hw/nvram/nrf51_nvm.h  |   64 ++
 include/qom/cpu.h |   16 +-
 linux-user/aarch64/target_syscall.h   |2 +
 target/arm/cpu.h  |   12 +-
 exec.c|   10 +-
 hw/arm/armsse.c   | 1241 +
 hw/arm/armv7m.c   |   23 +-
 hw/arm/boot.c |4 -
 hw/arm/iotkit.c   |  759 
 hw/arm/mps2-tz.c  |  121 +++-
 hw/arm/nrf51_soc.c