[Qemu-devel] [PATCH] MIPS Initial support of Godson-3a multicore CPU
Signed-off-by: Jin Guojie jinguo...@loongson.cn Reviewed-by: Gao Xiang gaoxi...@ict.ac.cn Reviewed-by: Chen Huacai zltjiang...@gmail.com A patch for Godson-3a CPU simulation. Godson-3a is a newly developed MIPS-III like, multicore CPU by ICT, China. We believe this patch could be helpful for other Godson developers. For you review. Any comment is welcomed. Jin Guojie www.loongson.cn --- Makefile.target |2 +- hw/mips_godson3a.c | 507 ++ target-mips/mips-defs.h |4 +- target-mips/translate_init.c | 26 +++ 4 files changed, 536 insertions(+), 3 deletions(-) create mode 100755 hw/mips_godson3a.c diff --git a/Makefile.target b/Makefile.target index 91e6e74..8f29aeb 100644 --- a/Makefile.target +++ b/Makefile.target @@ -230,7 +230,7 @@ obj-ppc-y += xilinx_timer.o obj-ppc-y += xilinx_uartlite.o obj-ppc-y += xilinx_ethlite.o -obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o +obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o mips_godson3a.o obj-mips-y += mips_addr.o mips_timer.o mips_int.o obj-mips-y += vga.o i8259.o obj-mips-y += g364fb.o jazz_led.o diff --git a/hw/mips_godson3a.c b/hw/mips_godson3a.c new file mode 100755 index 000..4085db2 --- /dev/null +++ b/hw/mips_godson3a.c @@ -0,0 +1,507 @@ +/* + * QEMU godson 3a developing board support + * + * Copyright (c) 2009 Gao Xiang (gaoxi...@ict.ac.cn) + * Copyright (c) 2010 Jin Guojie (jinguo...@loongson.cn) + * This code is licensed under the GNU GPL v2. + */ + +/* + * Godson 3a developing board is based on ICT/ST Godson-3a. + * Godson-3a CPU is a MIPS-III like, multicore processor. + * It can be configured to contain 4 or 8 cores. Every 4 + * cores are grouped into one on-chip 'node'. SMP mechanism + * is supported by Godson IPI(inter-processors interrupt) + * specification. + * + * Godson 3a CPU intro: + * http://en.wikipedia.org/wiki/Loongson + * + * Godson 3a user manual: + * http://www.loongsondeveloper.com/doc/Loongson3AUserGuide.pdf + */ +#include hw.h +#include mips.h +#include pc.h +#include isa.h +#include net.h +#include sysemu.h +#include boards.h +#include ide.h +#include mips-bios.h +#include elf.h +#include loader.h +#include blockdev.h +#include mips_cpudevs.h +#include mc146818rtc.h + +static target_ulong PHYS_TO_VIRT(target_ulong phys) +{ +if (smp_cpus 1) +return ((phys) | 0x9800ULL); +else +return ((phys) | ~(target_ulong)0x7fff); +} + +#define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x8000)) + +#define MAX_IDE_BUS 2 + +static const int ide_iobase[2] = { 0x1f0, 0x170 }; +static const int ide_iobase2[2] = { 0x3f6, 0x376 }; +static const int ide_irq[2] = { 14, 15 }; + +static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; + +static PITState *pit; /* PIT i8254 */ + +/* i8254 PIT is attached to the IRQ0 at PIC i8259 */ + +static struct _loaderparams { +int ram_size; +const char *kernel_filename; +const char *kernel_cmdline; +const char *initrd_filename; +} loaderparams; + +static void mips_qemu_writel (void *opaque, target_phys_addr_t addr, + uint32_t val) +{ +if ((addr 0x) == 0 val == 42) +qemu_system_reset_request(); +else if ((addr 0x) == 4 val == 42) +qemu_system_shutdown_request(); +} + +static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr) +{ +return 0; +} + +static CPUWriteMemoryFunc *mips_qemu_write[] = { +mips_qemu_writel, +mips_qemu_writel, +mips_qemu_writel, +}; + +static CPUReadMemoryFunc *mips_qemu_read[] = { +mips_qemu_readl, +mips_qemu_readl, +mips_qemu_readl, +}; + +static int mips_qemu_iomemtype = 0; + +typedef struct ResetData { +CPUState *env; +uint64_t vector; +} ResetData; + +static int64_t load_kernel (CPUState *env) +{ +int64_t entry, kernel_high; +long kernel_size, initrd_size, params_size; +ram_addr_t initrd_offset; +uint32_t *params_buf; +int big_endian; + +#ifdef TARGET_WORDS_BIGENDIAN +big_endian = 1; +#else +big_endian = 0; +#endif + +kernel_size = load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys, NULL, + (uint64_t *)entry, NULL, (uint64_t *)kernel_high, + big_endian, ELF_MACHINE, 1); +if (kernel_size = 0) { +if ((entry ~0x7fffULL) == 0x8000) +entry = (int32_t)entry; +env-active_tc.PC = entry; +env = first_cpu; +} else { +fprintf(stderr, qemu: could not load kernel '%s'\n, +loaderparams.kernel_filename); +exit(1); +} + +/* load initrd */ +initrd_size = 0; +initrd_offset = 0; +if (loaderparams.initrd_filename) { +initrd_size = get_image_size (loaderparams.initrd_filename); + if (initrd_size 0) { + if(initrd_size 0x1000) + initrd_offset = 0x100; +
Re: [Qemu-devel] [PATCH] MIPS Initial support of Godson-3a multicore CPU
1, signed-off-by and reviewed-by should put after the introduction and before the code, not at first. 2, You'd better split the big patch to 2~3 small patches, E.g. CPU definition and board emulation should be split. The format of email title will be [Patch 0/3], [Patch 1/3] and so on. [Patch 0/3] give a general introduction and others are real patches. 3, You should tell us how to test you code. E.g., you should provide PMON/BIOS, OS kernel or tell us how to build them in [patch 0/3]. For more information, you can search for my patch series about Loongson-2E. Good luck! Huacai Chen On Tue, Dec 7, 2010 at 5:32 PM, Jin Guojie jinguo...@loongson.cn wrote: Signed-off-by: Jin Guojie jinguo...@loongson.cn Reviewed-by: Gao Xiang gaoxi...@ict.ac.cn Reviewed-by: Chen Huacai zltjiang...@gmail.com A patch for Godson-3a CPU simulation. Godson-3a is a newly developed MIPS-III like, multicore CPU by ICT, China. We believe this patch could be helpful for other Godson developers. For you review. Any comment is welcomed. Jin Guojie www.loongson.cn --- Makefile.target | 2 +- hw/mips_godson3a.c | 507 ++ target-mips/mips-defs.h | 4 +- target-mips/translate_init.c | 26 +++ 4 files changed, 536 insertions(+), 3 deletions(-) create mode 100755 hw/mips_godson3a.c diff --git a/Makefile.target b/Makefile.target index 91e6e74..8f29aeb 100644 --- a/Makefile.target +++ b/Makefile.target @@ -230,7 +230,7 @@ obj-ppc-y += xilinx_timer.o obj-ppc-y += xilinx_uartlite.o obj-ppc-y += xilinx_ethlite.o -obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o +obj-mips-y = mips_r4k.o mips_jazz.o mips_malta.o mips_mipssim.o mips_godson3a.o obj-mips-y += mips_addr.o mips_timer.o mips_int.o obj-mips-y += vga.o i8259.o obj-mips-y += g364fb.o jazz_led.o diff --git a/hw/mips_godson3a.c b/hw/mips_godson3a.c new file mode 100755 index 000..4085db2 --- /dev/null +++ b/hw/mips_godson3a.c @@ -0,0 +1,507 @@ +/* + * QEMU godson 3a developing board support + * + * Copyright (c) 2009 Gao Xiang (gaoxi...@ict.ac.cn) + * Copyright (c) 2010 Jin Guojie (jinguo...@loongson.cn) + * This code is licensed under the GNU GPL v2. + */ + +/* + * Godson 3a developing board is based on ICT/ST Godson-3a. + * Godson-3a CPU is a MIPS-III like, multicore processor. + * It can be configured to contain 4 or 8 cores. Every 4 + * cores are grouped into one on-chip 'node'. SMP mechanism + * is supported by Godson IPI(inter-processors interrupt) + * specification. + * + * Godson 3a CPU intro: + * http://en.wikipedia.org/wiki/Loongson + * + * Godson 3a user manual: + * http://www.loongsondeveloper.com/doc/Loongson3AUserGuide.pdf + */ +#include hw.h +#include mips.h +#include pc.h +#include isa.h +#include net.h +#include sysemu.h +#include boards.h +#include ide.h +#include mips-bios.h +#include elf.h +#include loader.h +#include blockdev.h +#include mips_cpudevs.h +#include mc146818rtc.h + +static target_ulong PHYS_TO_VIRT(target_ulong phys) +{ + if (smp_cpus 1) + return ((phys) | 0x9800ULL); + else + return ((phys) | ~(target_ulong)0x7fff); +} + +#define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x8000)) + +#define MAX_IDE_BUS 2 + +static const int ide_iobase[2] = { 0x1f0, 0x170 }; +static const int ide_iobase2[2] = { 0x3f6, 0x376 }; +static const int ide_irq[2] = { 14, 15 }; + +static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; + +static PITState *pit; /* PIT i8254 */ + +/* i8254 PIT is attached to the IRQ0 at PIC i8259 */ + +static struct _loaderparams { + int ram_size; + const char *kernel_filename; + const char *kernel_cmdline; + const char *initrd_filename; +} loaderparams; + +static void mips_qemu_writel (void *opaque, target_phys_addr_t addr, + uint32_t val) +{ + if ((addr 0x) == 0 val == 42) + qemu_system_reset_request(); + else if ((addr 0x) == 4 val == 42) + qemu_system_shutdown_request(); +} + +static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr) +{ + return 0; +} + +static CPUWriteMemoryFunc *mips_qemu_write[] = { + mips_qemu_writel, + mips_qemu_writel, + mips_qemu_writel, +}; + +static CPUReadMemoryFunc *mips_qemu_read[] = { + mips_qemu_readl, + mips_qemu_readl, + mips_qemu_readl, +}; + +static int mips_qemu_iomemtype = 0; + +typedef struct ResetData { + CPUState *env; + uint64_t vector; +} ResetData; + +static int64_t load_kernel (CPUState *env) +{ + int64_t entry, kernel_high; + long kernel_size, initrd_size, params_size; + ram_addr_t initrd_offset; + uint32_t *params_buf; + int big_endian; + +#ifdef TARGET_WORDS_BIGENDIAN + big_endian = 1; +#else + big_endian = 0; +#endif + + kernel_size =
Re: [Qemu-devel] [patch] MIPS Initial support of Godson-3a multicore CPU
I think you'd better configure your smtp account and then use git send-email .patch to send patchs. In this way maintainer and other developers can easily review and comment your patch. Suggest you resend it. On Wed, Dec 1, 2010 at 11:10 AM, Jin Guojie guojie@gmail.com wrote: Aurelien, Attached is a patch for Godson-3a CPU support. Godson-3a is a newly developed MIPS-III like, multicore CPU by ICT, China. For you review. Any comment is welcomed. Jin Guojie www.loongson.cn -- Huacai Chen
[Qemu-devel] [patch] MIPS Initial support of Godson-3a multicore CPU
Aurelien, Attached is a patch for Godson-3a CPU support. Godson-3a is a newly developed MIPS-III like, multicore CPU by ICT, China. For you review. Any comment is welcomed. Jin Guojie www.loongson.cn 0001-MIPS-Initial-support-of-Godson-3a-multicore-CPU.patch Description: Binary data