Re: [Qemu-devel] [PATCH] intel-iommu: Accept 64-bit writes to FEADDR

[Peter Xu]

On Sat, Feb 17, 2018 at 12:26:19PM +0100, Jan Kiszka wrote:
> From: Jan Kiszka 
> 
> Xen is doing this [1] and currently triggers an abort.
> 
> [1] 
> http://xenbits.xenproject.org/gitweb/?p=xen.git;a=blob;f=xen/drivers/passthrough/vtd/iommu.c;h=daaed0abbdd06b6ba3d948ea103aadf02651e83c;hb=refs/heads/master#l1108
> 
> Reported-by: Luis Lloret 
> Signed-off-by: Jan Kiszka 
> ---
>  hw/i386/intel_iommu.c | 7 ++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 2e841cde27..b61d0da270 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -2129,7 +2129,12 @@ static void vtd_mem_write(void *opaque, hwaddr addr,
>  
>  /* Fault Event Address Register, 32-bit */
>  case DMAR_FEADDR_REG:
> -assert(size == 4);
> +/*
> + * While the register is 32-bit only, some guests (Xen...) write to 
> it
> + * with 64-bit. Ignore the upper part, that's likely what the 
> hardware
> + * does as well (plus the upper part is not used by our model 
> anyway).
> + */
> +assert(size >= 4);
>  vtd_set_long(s, addr, val);
>  break;

(Sorry for the late response due to Chinese Spring Festival)

I agree with the problem there, but do we still better provide a
conditional vtd_set_quad()?  Since from the spec 10.4.13 the upper 32
bits may still be used when x2apic (Extended Interrupt Mode) is
enabled?

Thanks,

-- 
Peter Xu

[Qemu-devel] [PATCH] intel-iommu: Accept 64-bit writes to FEADDR

[Jan Kiszka]

From: Jan Kiszka 

Xen is doing this [1] and currently triggers an abort.

[1] 
http://xenbits.xenproject.org/gitweb/?p=xen.git;a=blob;f=xen/drivers/passthrough/vtd/iommu.c;h=daaed0abbdd06b6ba3d948ea103aadf02651e83c;hb=refs/heads/master#l1108

Reported-by: Luis Lloret 
Signed-off-by: Jan Kiszka 
---
 hw/i386/intel_iommu.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 2e841cde27..b61d0da270 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2129,7 +2129,12 @@ static void vtd_mem_write(void *opaque, hwaddr addr,
 
 /* Fault Event Address Register, 32-bit */
 case DMAR_FEADDR_REG:
-assert(size == 4);
+/*
+ * While the register is 32-bit only, some guests (Xen...) write to it
+ * with 64-bit. Ignore the upper part, that's likely what the hardware
+ * does as well (plus the upper part is not used by our model anyway).
+ */
+assert(size >= 4);
 vtd_set_long(s, addr, val);
 break;
 
-- 
2.13.6