subject:"\[Qemu\-devel\] \[PATCH\] target\-sh4\: Use new qemu

Re: [Qemu-devel] [PATCH] target-sh4: Use new qemu_ld/st opcodes

2013-12-13 Thread Alex Bennée


aurel...@aurel32.net writes:

 Signed-off-by: Aurelien Jarno aurel...@aurel32.net
 ---
  target-sh4/translate.c |  167 
 ++--
  1 file changed, 90 insertions(+), 77 deletions(-)

 diff --git a/target-sh4/translate.c b/target-sh4/translate.c
 index 2272eb0..87f532a 100644
 --- a/target-sh4/translate.c
 +++ b/target-sh4/translate.c
 @@ -464,7 +464,7 @@ static void _decode_opc(DisasContext * ctx)
   {
   TCGv addr = tcg_temp_new();
   tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4);
 - tcg_gen_qemu_st32(REG(B7_4), addr, ctx-memidx);
 +tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx-memidx, MO_TEUL);
   tcg_temp_free(addr);
snip

There seems to be a fix of tabs and spaces in that patch.

-- 
Alex Bennée
QEMU/KVM Hacker for Linaro

Re: [Qemu-devel] [PATCH] target-sh4: Use new qemu_ld/st opcodes

2013-12-13 Thread Aurelien Jarno

On Fri, Dec 13, 2013 at 09:36:13AM +, Alex Bennée wrote:
 
 aurel...@aurel32.net writes:
 
  Signed-off-by: Aurelien Jarno aurel...@aurel32.net
  ---
   target-sh4/translate.c |  167 
  ++--
   1 file changed, 90 insertions(+), 77 deletions(-)
 
  diff --git a/target-sh4/translate.c b/target-sh4/translate.c
  index 2272eb0..87f532a 100644
  --- a/target-sh4/translate.c
  +++ b/target-sh4/translate.c
  @@ -464,7 +464,7 @@ static void _decode_opc(DisasContext * ctx)
  {
  TCGv addr = tcg_temp_new();
  tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4);
  -   tcg_gen_qemu_st32(REG(B7_4), addr, ctx-memidx);
  +tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx-memidx, MO_TEUL);
  tcg_temp_free(addr);
 snip
 
 There seems to be a fix of tabs and spaces in that patch.
 

Indeed, this file is partly tabs indented for historical reasons, so
they are changed to space in the patch, to conform to the QEMU coding
style. AFAIK there is a consensus that things should be done that way.

-- 
Aurelien Jarno  GPG: 1024D/F1BCDB73
aurel...@aurel32.net http://www.aurel32.net

[Qemu-devel] [PATCH] target-sh4: Use new qemu_ld/st opcodes

2013-12-12 Thread Aurelien Jarno

Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
 target-sh4/translate.c |  167 ++--
 1 file changed, 90 insertions(+), 77 deletions(-)

diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 2272eb0..87f532a 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -464,7 +464,7 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4);
-   tcg_gen_qemu_st32(REG(B7_4), addr, ctx-memidx);
+tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx-memidx, MO_TEUL);
tcg_temp_free(addr);
}
return;
@@ -472,7 +472,7 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4);
-   tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx-memidx);
+tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx-memidx, MO_TESL);
tcg_temp_free(addr);
}
return;
@@ -482,14 +482,14 @@ static void _decode_opc(DisasContext * ctx)
 case 0x9000:   /* mov.w @(disp,PC),Rn */
{
TCGv addr = tcg_const_i32(ctx-pc + 4 + B7_0 * 2);
-   tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx-memidx);
+tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx-memidx, MO_TESW);
tcg_temp_free(addr);
}
return;
 case 0xd000:   /* mov.l @(disp,PC),Rn */
{
TCGv addr = tcg_const_i32((ctx-pc + 4 + B7_0 * 4)  ~3);
-   tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx-memidx);
+tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx-memidx, MO_TESL);
tcg_temp_free(addr);
}
return;
@@ -516,28 +516,29 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_mov_i32(REG(B11_8), REG(B7_4));
return;
 case 0x2000:   /* mov.b Rm,@Rn */
-   tcg_gen_qemu_st8(REG(B7_4), REG(B11_8), ctx-memidx);
+tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx-memidx, MO_UB);
return;
 case 0x2001:   /* mov.w Rm,@Rn */
-   tcg_gen_qemu_st16(REG(B7_4), REG(B11_8), ctx-memidx);
+tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx-memidx, MO_TEUW);
return;
 case 0x2002:   /* mov.l Rm,@Rn */
-   tcg_gen_qemu_st32(REG(B7_4), REG(B11_8), ctx-memidx);
+tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx-memidx, MO_TEUL);
return;
 case 0x6000:   /* mov.b @Rm,Rn */
-   tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx-memidx);
+tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx-memidx, MO_SB);
return;
 case 0x6001:   /* mov.w @Rm,Rn */
-   tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx-memidx);
+tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx-memidx, MO_TESW);
return;
 case 0x6002:   /* mov.l @Rm,Rn */
-   tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx-memidx);
+tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx-memidx, MO_TESL);
return;
 case 0x2004:   /* mov.b Rm,@-Rn */
{
TCGv addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 1);
-   tcg_gen_qemu_st8(REG(B7_4), addr, ctx-memidx); /* might cause 
re-execution */
+/* might cause re-execution */
+tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx-memidx, MO_UB);
tcg_gen_mov_i32(REG(B11_8), addr);  /* modify 
register status */
tcg_temp_free(addr);
}
@@ -546,7 +547,7 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 2);
-   tcg_gen_qemu_st16(REG(B7_4), addr, ctx-memidx);
+tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx-memidx, MO_TEUW);
tcg_gen_mov_i32(REG(B11_8), addr);
tcg_temp_free(addr);
}
@@ -555,22 +556,22 @@ static void _decode_opc(DisasContext * ctx)
{
TCGv addr = tcg_temp_new();
tcg_gen_subi_i32(addr, REG(B11_8), 4);
-   tcg_gen_qemu_st32(REG(B7_4), addr, ctx-memidx);
+tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx-memidx, MO_TEUL);
tcg_gen_mov_i32(REG(B11_8), addr);
}
return;
 case 0x6004:   /* mov.b @Rm+,Rn */
-   tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx-memidx);
+tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx-memidx, MO_SB);
if ( B11_8 != B7_4 )
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1);
return;
 case 0x6005:   /* mov.w @Rm+,Rn */
-   tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx-memidx);
+tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx-memidx, MO_TESW);
if ( B11_8 != B7_4 )
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
return;
 case 0x6006:

Re: [Qemu-devel] [PATCH] target-sh4: Use new qemu_ld/st opcodes

2013-12-12 Thread Edgar E. Iglesias

On Fri, Dec 13, 2013 at 01:07:06AM +0100, Aurelien Jarno wrote:
 Signed-off-by: Aurelien Jarno aurel...@aurel32.net

Reviewed-by: Edgar E. Iglesias edgar.igles...@gmail.com


 ---
  target-sh4/translate.c |  167 
 ++--
  1 file changed, 90 insertions(+), 77 deletions(-)
 
 diff --git a/target-sh4/translate.c b/target-sh4/translate.c
 index 2272eb0..87f532a 100644
 --- a/target-sh4/translate.c
 +++ b/target-sh4/translate.c
 @@ -464,7 +464,7 @@ static void _decode_opc(DisasContext * ctx)
   {
   TCGv addr = tcg_temp_new();
   tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4);
 - tcg_gen_qemu_st32(REG(B7_4), addr, ctx-memidx);
 +tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx-memidx, MO_TEUL);
   tcg_temp_free(addr);
   }
   return;
 @@ -472,7 +472,7 @@ static void _decode_opc(DisasContext * ctx)
   {
   TCGv addr = tcg_temp_new();
   tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4);
 - tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx-memidx);
 +tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx-memidx, MO_TESL);
   tcg_temp_free(addr);
   }
   return;
 @@ -482,14 +482,14 @@ static void _decode_opc(DisasContext * ctx)
  case 0x9000: /* mov.w @(disp,PC),Rn */
   {
   TCGv addr = tcg_const_i32(ctx-pc + 4 + B7_0 * 2);
 - tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx-memidx);
 +tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx-memidx, MO_TESW);
   tcg_temp_free(addr);
   }
   return;
  case 0xd000: /* mov.l @(disp,PC),Rn */
   {
   TCGv addr = tcg_const_i32((ctx-pc + 4 + B7_0 * 4)  ~3);
 - tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx-memidx);
 +tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx-memidx, MO_TESL);
   tcg_temp_free(addr);
   }
   return;
 @@ -516,28 +516,29 @@ static void _decode_opc(DisasContext * ctx)
   tcg_gen_mov_i32(REG(B11_8), REG(B7_4));
   return;
  case 0x2000: /* mov.b Rm,@Rn */
 - tcg_gen_qemu_st8(REG(B7_4), REG(B11_8), ctx-memidx);
 +tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx-memidx, MO_UB);
   return;
  case 0x2001: /* mov.w Rm,@Rn */
 - tcg_gen_qemu_st16(REG(B7_4), REG(B11_8), ctx-memidx);
 +tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx-memidx, MO_TEUW);
   return;
  case 0x2002: /* mov.l Rm,@Rn */
 - tcg_gen_qemu_st32(REG(B7_4), REG(B11_8), ctx-memidx);
 +tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx-memidx, MO_TEUL);
   return;
  case 0x6000: /* mov.b @Rm,Rn */
 - tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx-memidx);
 +tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx-memidx, MO_SB);
   return;
  case 0x6001: /* mov.w @Rm,Rn */
 - tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx-memidx);
 +tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx-memidx, MO_TESW);
   return;
  case 0x6002: /* mov.l @Rm,Rn */
 - tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx-memidx);
 +tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx-memidx, MO_TESL);
   return;
  case 0x2004: /* mov.b Rm,@-Rn */
   {
   TCGv addr = tcg_temp_new();
   tcg_gen_subi_i32(addr, REG(B11_8), 1);
 - tcg_gen_qemu_st8(REG(B7_4), addr, ctx-memidx); /* might cause 
 re-execution */
 +/* might cause re-execution */
 +tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx-memidx, MO_UB);
   tcg_gen_mov_i32(REG(B11_8), addr);  /* modify 
 register status */
   tcg_temp_free(addr);
   }
 @@ -546,7 +547,7 @@ static void _decode_opc(DisasContext * ctx)
   {
   TCGv addr = tcg_temp_new();
   tcg_gen_subi_i32(addr, REG(B11_8), 2);
 - tcg_gen_qemu_st16(REG(B7_4), addr, ctx-memidx);
 +tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx-memidx, MO_TEUW);
   tcg_gen_mov_i32(REG(B11_8), addr);
   tcg_temp_free(addr);
   }
 @@ -555,22 +556,22 @@ static void _decode_opc(DisasContext * ctx)
   {
   TCGv addr = tcg_temp_new();
   tcg_gen_subi_i32(addr, REG(B11_8), 4);
 - tcg_gen_qemu_st32(REG(B7_4), addr, ctx-memidx);
 +tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx-memidx, MO_TEUL);
   tcg_gen_mov_i32(REG(B11_8), addr);
   }
   return;
  case 0x6004: /* mov.b @Rm+,Rn */
 - tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx-memidx);
 +tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx-memidx, MO_SB);
   if ( B11_8 != B7_4 )
   tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1);
   return;
  case 0x6005: /* mov.w @Rm+,Rn */
 - tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx-memidx);
 +tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx-memidx, MO_TESW);
   if ( B11_8 != B7_4 )

Re: [Qemu-devel] [PATCH] target-sh4: Use new qemu_ld/st opcodes

Re: [Qemu-devel] [PATCH] target-sh4: Use new qemu_ld/st opcodes

[Qemu-devel] [PATCH] target-sh4: Use new qemu_ld/st opcodes

Re: [Qemu-devel] [PATCH] target-sh4: Use new qemu_ld/st opcodes

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