Re: [Qemu-devel] [PATCH 0/2 v2] pc: inform SeaBIOS where 64-bit PCI hole begins
Hi, So maybe design that with memory hotplug in mind? Such as adding a new qemu-specific type QEMU_RAM_HOTPLUG? Which seabios could use to reserve the memory (but not add it to the e820 table for the guest)? It will do job too. But extending semantics of standard table would be confusing. Yes, Seabios will filter it out but it doesn't make table less confusing. Was just thinking that it might be easier that way if we need e820 entries for hotplug memory address space _anyway_. I'd prefer having a dedicated interface for it as a more clean solution. Agree. cheers, Gerd
Re: [Qemu-devel] [PATCH 0/2 v2] pc: inform SeaBIOS where 64-bit PCI hole begins
On Mon, 04 Nov 2013 13:48:03 +0100 Gerd Hoffmann kra...@redhat.com wrote: Hi, So maybe design that with memory hotplug in mind? Such as adding a new qemu-specific type QEMU_RAM_HOTPLUG? Which seabios could use to reserve the memory (but not add it to the e820 table for the guest)? It will do job too. But extending semantics of standard table would be confusing. Yes, Seabios will filter it out but it doesn't make table less confusing. Was just thinking that it might be easier that way if we need e820 entries for hotplug memory address space _anyway_. I don't think that we need e820 entries for hotplug memory reserved space as e820 should. In case present at boot hotpluggable DIMMs would be needed in E820, we can add them as usual E820_RAM entries. But regardless of what we do here it might be good keep option of adding non standard entries in future, by filtering out unknown types in SeaBIOS. I'd prefer having a dedicated interface for it as a more clean solution. Agree. So back to naming question, would you agree to renaming fw_cfg to the last Michael's suggestion reserved-memory-end? cheers, Gerd
Re: [Qemu-devel] [PATCH 0/2 v2] pc: inform SeaBIOS where 64-bit PCI hole begins
On Mo, 2013-11-04 at 15:35 +0100, Igor Mammedov wrote: On Mon, 04 Nov 2013 13:48:03 +0100 Gerd Hoffmann kra...@redhat.com wrote: Hi, So maybe design that with memory hotplug in mind? Such as adding a new qemu-specific type QEMU_RAM_HOTPLUG? Which seabios could use to reserve the memory (but not add it to the e820 table for the guest)? It will do job too. But extending semantics of standard table would be confusing. Yes, Seabios will filter it out but it doesn't make table less confusing. Was just thinking that it might be easier that way if we need e820 entries for hotplug memory address space _anyway_. I don't think that we need e820 entries for hotplug memory reserved space as e820 should. In case present at boot hotpluggable DIMMs would be needed in E820, we can add them as usual E820_RAM entries. But regardless of what we do here it might be good keep option of adding non standard entries in future, by filtering out unknown types in SeaBIOS. I'd prefer having a dedicated interface for it as a more clean solution. Agree. So back to naming question, would you agree to renaming fw_cfg to the last Michael's suggestion reserved-memory-end? Fine with me. cheers, Gerd
Re: [Qemu-devel] [PATCH 0/2 v2] pc: inform SeaBIOS where 64-bit PCI hole begins
Hi, Well, BIOS have to know where it could start 64-bit BARs mappings and telling it explicitly where, looks like a good way to do it. As far as I can tell, BIOS can start any mappings anywhere it wants to as long as they don't overlap anything else. What is has to know is what hardware is there. Use case is memory hotplug. Once we generate the acpi tables in qemu seabios doesn't need to know anything about hotpluggable memory slots. Still it better should not map 64bit pci bars into that address space. So it IMHO makes sense to give seabios a hit where it should map the 64bit pci bars. cheers, Gerd
Re: [Qemu-devel] [PATCH 0/2 v2] pc: inform SeaBIOS where 64-bit PCI hole begins
On Tue, 29 Oct 2013 20:52:42 +0200 Michael S. Tsirkin m...@redhat.com wrote: On Tue, Oct 29, 2013 at 04:28:25PM +0100, Igor Mammedov wrote: On Tue, 29 Oct 2013 17:10:47 +0200 Michael S. Tsirkin m...@redhat.com wrote: On Tue, Oct 29, 2013 at 01:57:33PM +0100, Igor Mammedov wrote: * simplify PCI address space mapping into system address space, replacing code duplication in piix/q53 PCs with a helper function * add fw_cfg 'etc/pcimem64-minimum-address' to allow QEMU reserve additional address space before 64-bit PCI hole. Which will be need for reserving memory hotplug region in highmem. SeaBIOS counterpart: http://patchwork.ozlabs.org/patch/283623/ I'd like to see if we can figure out the migration issue with memory layout. It seems that there isn't migration issue here. Hmm earlier you thought there was - it's ok now? Because if we do, and get rid of the separate 64 bit region as a concept, exposing the start of this non-existent region in FW CFG will make very little sense IMHO. Well, BIOS have to know where it could start 64-bit BARs mappings and telling it explicitly where, looks like a good way to do it. As far as I can tell, BIOS can start any mappings anywhere it wants to as long as they don't overlap anything else. What is has to know is what hardware is there. lets suppose we are describing HW to Seabios (about which it doesn't really needs to know when we move ACPI tables into QEMU) 1. we inform Seabios where memory hotplug region ends (describing new hw) and name parameter etc/mem-hoplug-region-end and make appropriate change to Seabois so it would know about memory hotlug region. 2. than in several releases we decide to add another device that would reserve address space after memory hotplug region. That would require another modification of Seabios to teach it about new hardware so it could place 64-bit PCI mappings after it. So describing a new hardware each time will only increase amount of PV interfaces overtime, breaking old BIOSes and forcing us to maintain compatibility layers for old versions in Seabios and QEMU. Opposite approach in this series tries to minimize all above mentioned problems by providing Seabios with an explicit information that it needs to make correct 64-bit PCI BARs mappings and it won't introduce compatibility issues with Seabios if we reserve extra space behind memory hotlpug region in future. v2: * use negative priority to map PCI address space under RAM memory regions which allows simplify code by removing pci_hole pci_hole64 memory region aliases Series depends on: memory: Change MemoryRegion priorities from unsigned to signed: Git tree for testing: https://github.com/imammedo/qemu/commits/pcimem64-minimum-address-v2 Igor Mammedov (1): pc: add 'etc/pcimem64-minimum-address' fw_cfg interface to SeaBIOS Michael S. Tsirkin (1): pc: map PCI address space as catchall region for not mapped addresses hw/i386/pc.c | 28 hw/i386/pc_piix.c |2 -- hw/pci-host/piix.c| 27 +-- hw/pci-host/q35.c | 28 ++-- include/hw/i386/pc.h | 15 +++ include/hw/pci-host/q35.h |2 -- 6 files changed, 30 insertions(+), 72 deletions(-)
Re: [Qemu-devel] [PATCH 0/2 v2] pc: inform SeaBIOS where 64-bit PCI hole begins
On Tue, 29 Oct 2013 20:52:42 +0200 Michael S. Tsirkin m...@redhat.com wrote: On Tue, Oct 29, 2013 at 04:28:25PM +0100, Igor Mammedov wrote: On Tue, 29 Oct 2013 17:10:47 +0200 Michael S. Tsirkin m...@redhat.com wrote: On Tue, Oct 29, 2013 at 01:57:33PM +0100, Igor Mammedov wrote: * simplify PCI address space mapping into system address space, replacing code duplication in piix/q53 PCs with a helper function * add fw_cfg 'etc/pcimem64-minimum-address' to allow QEMU reserve additional address space before 64-bit PCI hole. Which will be need for reserving memory hotplug region in highmem. SeaBIOS counterpart: http://patchwork.ozlabs.org/patch/283623/ I'd like to see if we can figure out the migration issue with memory layout. It seems that there isn't migration issue here. Hmm earlier you thought there was - it's ok now? You've probably missed my reply http://www.mail-archive.com/qemu-devel@nongnu.org/msg199586.html it was error it test environment.
Re: [Qemu-devel] [PATCH 0/2 v2] pc: inform SeaBIOS where 64-bit PCI hole begins
On Wed, Oct 30, 2013 at 02:24:54PM +0100, Igor Mammedov wrote: On Tue, 29 Oct 2013 20:52:42 +0200 Michael S. Tsirkin m...@redhat.com wrote: On Tue, Oct 29, 2013 at 04:28:25PM +0100, Igor Mammedov wrote: On Tue, 29 Oct 2013 17:10:47 +0200 Michael S. Tsirkin m...@redhat.com wrote: On Tue, Oct 29, 2013 at 01:57:33PM +0100, Igor Mammedov wrote: * simplify PCI address space mapping into system address space, replacing code duplication in piix/q53 PCs with a helper function * add fw_cfg 'etc/pcimem64-minimum-address' to allow QEMU reserve additional address space before 64-bit PCI hole. Which will be need for reserving memory hotplug region in highmem. SeaBIOS counterpart: http://patchwork.ozlabs.org/patch/283623/ I'd like to see if we can figure out the migration issue with memory layout. It seems that there isn't migration issue here. Hmm earlier you thought there was - it's ok now? Because if we do, and get rid of the separate 64 bit region as a concept, exposing the start of this non-existent region in FW CFG will make very little sense IMHO. Well, BIOS have to know where it could start 64-bit BARs mappings and telling it explicitly where, looks like a good way to do it. As far as I can tell, BIOS can start any mappings anywhere it wants to as long as they don't overlap anything else. What is has to know is what hardware is there. lets suppose we are describing HW to Seabios (about which it doesn't really needs to know when we move ACPI tables into QEMU) 1. we inform Seabios where memory hotplug region ends (describing new hw) and name parameter etc/mem-hoplug-region-end and make appropriate change to Seabois so it would know about memory hotlug region. 2. than in several releases we decide to add another device that would reserve address space after memory hotplug region. That would require another modification of Seabios to teach it about new hardware so it could place 64-bit PCI mappings after it. So describing a new hardware each time will only increase amount of PV interfaces overtime, breaking old BIOSes and forcing us to maintain compatibility layers for old versions in Seabios and QEMU. I don't think we can predict the future. It seems just as likely that BIOS will need to drive the new hardware so it will not be enough to have start pci here. In particular, non-contiguous hotpluggable memory does not seem all that far-fetched, and we might want to put PCI devices in the holes that are left free. Maybe, if you want it make it kind of generic you can just say reserved-memory-end with the same value. Opposite approach in this series tries to minimize all above mentioned problems by providing Seabios with an explicit information that it needs to make correct 64-bit PCI BARs mappings and it won't introduce compatibility issues with Seabios if we reserve extra space behind memory hotlpug region in future. Point is that the value you expose has nothing to do with PCI. Yes BIOS might use it for that but interfaces need to tell what they are, not what they are used for. v2: * use negative priority to map PCI address space under RAM memory regions which allows simplify code by removing pci_hole pci_hole64 memory region aliases Series depends on: memory: Change MemoryRegion priorities from unsigned to signed: Git tree for testing: https://github.com/imammedo/qemu/commits/pcimem64-minimum-address-v2 Igor Mammedov (1): pc: add 'etc/pcimem64-minimum-address' fw_cfg interface to SeaBIOS Michael S. Tsirkin (1): pc: map PCI address space as catchall region for not mapped addresses hw/i386/pc.c | 28 hw/i386/pc_piix.c |2 -- hw/pci-host/piix.c| 27 +-- hw/pci-host/q35.c | 28 ++-- include/hw/i386/pc.h | 15 +++ include/hw/pci-host/q35.h |2 -- 6 files changed, 30 insertions(+), 72 deletions(-)
Re: [Qemu-devel] [PATCH 0/2 v2] pc: inform SeaBIOS where 64-bit PCI hole begins
Hi, I don't think we can predict the future. It seems just as likely that BIOS will need to drive the new hardware so it will not be enough to have start pci here. In particular, non-contiguous hotpluggable memory does not seem all that far-fetched, and we might want to put PCI devices in the holes that are left free. Maybe, if you want it make it kind of generic you can just say reserved-memory-end with the same value. What is the plan for handling e820 with memory hotplug btw? You've mentioned e820 entries for hotpluggable dimms present at boot are needed for some guests. I'm about to add a new e820 fw_cfg interface (see http://comments.gmane.org/gmane.comp.emulators.qemu/238860). So maybe design that with memory hotplug in mind? Such as adding a new qemu-specific type QEMU_RAM_HOTPLUG? Which seabios could use to reserve the memory (but not add it to the e820 table for the guest)? cheers, Gerd
Re: [Qemu-devel] [PATCH 0/2 v2] pc: inform SeaBIOS where 64-bit PCI hole begins
On Wed, 30 Oct 2013 15:33:35 +0100 Gerd Hoffmann kra...@redhat.com wrote: Hi, I don't think we can predict the future. It seems just as likely that BIOS will need to drive the new hardware so it will not be enough to have start pci here. In particular, non-contiguous hotpluggable memory does not seem all that far-fetched, and we might want to put PCI devices in the holes that are left free. Maybe, if you want it make it kind of generic you can just say reserved-memory-end with the same value. What is the plan for handling e820 with memory hotplug btw? There wasn't immediate plans for using e820 for hotplugged memory yet. You've mentioned e820 entries for hotpluggable dimms present at boot are needed for some guests. Windows guest are fine and do not require e820 entries for present hotplugged memory, automatically onlining memory devices described in ACPI. Linux guests see memory devices described in ACPI but do not online them automatically. I'm not sure how valid would be putting present hotplugged memory into e820 which is supposed to be static. It would be better if linux guests behave as windows, it could online memory regions in userspace (using udev) or fix kernel to do it at boot time after scanning ACPI devices. I'm about to add a new e820 fw_cfg interface (see http://comments.gmane.org/gmane.comp.emulators.qemu/238860). So maybe design that with memory hotplug in mind? Such as adding a new qemu-specific type QEMU_RAM_HOTPLUG? Which seabios could use to reserve the memory (but not add it to the e820 table for the guest)? It will do job too. But extending semantics of standard table would be confusing. Yes, Seabios will filter it out but it doesn't make table less confusing. I'd prefer having a dedicated interface for it as a more clean solution. cheers, Gerd
[Qemu-devel] [PATCH 0/2 v2] pc: inform SeaBIOS where 64-bit PCI hole begins
* simplify PCI address space mapping into system address space, replacing code duplication in piix/q53 PCs with a helper function * add fw_cfg 'etc/pcimem64-minimum-address' to allow QEMU reserve additional address space before 64-bit PCI hole. Which will be need for reserving memory hotplug region in highmem. SeaBIOS counterpart: http://patchwork.ozlabs.org/patch/283623/ v2: * use negative priority to map PCI address space under RAM memory regions which allows simplify code by removing pci_hole pci_hole64 memory region aliases Series depends on: memory: Change MemoryRegion priorities from unsigned to signed: Git tree for testing: https://github.com/imammedo/qemu/commits/pcimem64-minimum-address-v2 Igor Mammedov (1): pc: add 'etc/pcimem64-minimum-address' fw_cfg interface to SeaBIOS Michael S. Tsirkin (1): pc: map PCI address space as catchall region for not mapped addresses hw/i386/pc.c | 28 hw/i386/pc_piix.c |2 -- hw/pci-host/piix.c| 27 +-- hw/pci-host/q35.c | 28 ++-- include/hw/i386/pc.h | 15 +++ include/hw/pci-host/q35.h |2 -- 6 files changed, 30 insertions(+), 72 deletions(-)
Re: [Qemu-devel] [PATCH 0/2 v2] pc: inform SeaBIOS where 64-bit PCI hole begins
On Tue, Oct 29, 2013 at 01:57:33PM +0100, Igor Mammedov wrote: * simplify PCI address space mapping into system address space, replacing code duplication in piix/q53 PCs with a helper function * add fw_cfg 'etc/pcimem64-minimum-address' to allow QEMU reserve additional address space before 64-bit PCI hole. Which will be need for reserving memory hotplug region in highmem. SeaBIOS counterpart: http://patchwork.ozlabs.org/patch/283623/ I'd like to see if we can figure out the migration issue with memory layout. Because if we do, and get rid of the separate 64 bit region as a concept, exposing the start of this non-existent region in FW CFG will make very little sense IMHO. v2: * use negative priority to map PCI address space under RAM memory regions which allows simplify code by removing pci_hole pci_hole64 memory region aliases Series depends on: memory: Change MemoryRegion priorities from unsigned to signed: Git tree for testing: https://github.com/imammedo/qemu/commits/pcimem64-minimum-address-v2 Igor Mammedov (1): pc: add 'etc/pcimem64-minimum-address' fw_cfg interface to SeaBIOS Michael S. Tsirkin (1): pc: map PCI address space as catchall region for not mapped addresses hw/i386/pc.c | 28 hw/i386/pc_piix.c |2 -- hw/pci-host/piix.c| 27 +-- hw/pci-host/q35.c | 28 ++-- include/hw/i386/pc.h | 15 +++ include/hw/pci-host/q35.h |2 -- 6 files changed, 30 insertions(+), 72 deletions(-)
Re: [Qemu-devel] [PATCH 0/2 v2] pc: inform SeaBIOS where 64-bit PCI hole begins
On Tue, 29 Oct 2013 17:10:47 +0200 Michael S. Tsirkin m...@redhat.com wrote: On Tue, Oct 29, 2013 at 01:57:33PM +0100, Igor Mammedov wrote: * simplify PCI address space mapping into system address space, replacing code duplication in piix/q53 PCs with a helper function * add fw_cfg 'etc/pcimem64-minimum-address' to allow QEMU reserve additional address space before 64-bit PCI hole. Which will be need for reserving memory hotplug region in highmem. SeaBIOS counterpart: http://patchwork.ozlabs.org/patch/283623/ I'd like to see if we can figure out the migration issue with memory layout. It seems that there isn't migration issue here. Because if we do, and get rid of the separate 64 bit region as a concept, exposing the start of this non-existent region in FW CFG will make very little sense IMHO. Well, BIOS have to know where it could start 64-bit BARs mappings and telling it explicitly where, looks like a good way to do it. v2: * use negative priority to map PCI address space under RAM memory regions which allows simplify code by removing pci_hole pci_hole64 memory region aliases Series depends on: memory: Change MemoryRegion priorities from unsigned to signed: Git tree for testing: https://github.com/imammedo/qemu/commits/pcimem64-minimum-address-v2 Igor Mammedov (1): pc: add 'etc/pcimem64-minimum-address' fw_cfg interface to SeaBIOS Michael S. Tsirkin (1): pc: map PCI address space as catchall region for not mapped addresses hw/i386/pc.c | 28 hw/i386/pc_piix.c |2 -- hw/pci-host/piix.c| 27 +-- hw/pci-host/q35.c | 28 ++-- include/hw/i386/pc.h | 15 +++ include/hw/pci-host/q35.h |2 -- 6 files changed, 30 insertions(+), 72 deletions(-)
Re: [Qemu-devel] [PATCH 0/2 v2] pc: inform SeaBIOS where 64-bit PCI hole begins
On Tue, Oct 29, 2013 at 04:28:25PM +0100, Igor Mammedov wrote: On Tue, 29 Oct 2013 17:10:47 +0200 Michael S. Tsirkin m...@redhat.com wrote: On Tue, Oct 29, 2013 at 01:57:33PM +0100, Igor Mammedov wrote: * simplify PCI address space mapping into system address space, replacing code duplication in piix/q53 PCs with a helper function * add fw_cfg 'etc/pcimem64-minimum-address' to allow QEMU reserve additional address space before 64-bit PCI hole. Which will be need for reserving memory hotplug region in highmem. SeaBIOS counterpart: http://patchwork.ozlabs.org/patch/283623/ I'd like to see if we can figure out the migration issue with memory layout. It seems that there isn't migration issue here. Hmm earlier you thought there was - it's ok now? Because if we do, and get rid of the separate 64 bit region as a concept, exposing the start of this non-existent region in FW CFG will make very little sense IMHO. Well, BIOS have to know where it could start 64-bit BARs mappings and telling it explicitly where, looks like a good way to do it. As far as I can tell, BIOS can start any mappings anywhere it wants to as long as they don't overlap anything else. What is has to know is what hardware is there. v2: * use negative priority to map PCI address space under RAM memory regions which allows simplify code by removing pci_hole pci_hole64 memory region aliases Series depends on: memory: Change MemoryRegion priorities from unsigned to signed: Git tree for testing: https://github.com/imammedo/qemu/commits/pcimem64-minimum-address-v2 Igor Mammedov (1): pc: add 'etc/pcimem64-minimum-address' fw_cfg interface to SeaBIOS Michael S. Tsirkin (1): pc: map PCI address space as catchall region for not mapped addresses hw/i386/pc.c | 28 hw/i386/pc_piix.c |2 -- hw/pci-host/piix.c| 27 +-- hw/pci-host/q35.c | 28 ++-- include/hw/i386/pc.h | 15 +++ include/hw/pci-host/q35.h |2 -- 6 files changed, 30 insertions(+), 72 deletions(-)
