Re: [Qemu-devel] [PATCH 00/19] Add Cortex-M33 and mps2-an505 board model

[no-reply]

Hi,

This series failed docker-quick@centos6 build test. Please find the testing 
commands and
their output below. If you have Docker installed, you can probably reproduce it
locally.

Type: series
Message-id: 20180220180325.29818-1-peter.mayd...@linaro.org
Subject: [Qemu-devel] [PATCH 00/19] Add Cortex-M33 and mps2-an505 board model

=== TEST SCRIPT BEGIN ===
#!/bin/bash
set -e
git submodule update --init dtc
# Let docker tests dump environment info
export SHOW_ENV=1
export J=8
time make docker-test-quick@centos6
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
7d3e83003a mps2-an505: New board model: MPS2 with AN505 Cortex-M33 FPGA image
008d624b9c hw/arm/iotkit: Model Arm IOT Kit
c9fe4b0446 hw/misc/iotkit-secctl: Add remaining simple registers
3e31bda208 hw/misc/iotkit-secctl: Add handling for PPCs
49891ade94 hw/misc/iotkit-secctl: Arm IoT Kit security controller initial 
skeleton
01484af03f hw/misc/tz-ppc: Model TrustZone peripheral protection controller
21a39893f5 hw/misc/mps2-fpgaio: FPGA control block for MPS2 AN505
58df172c0a hw/core/split-irq: Device that splits IRQ lines
93f8bafcf7 qdev: Add new qdev_init_gpio_in_named_with_opaque()
e8b01923f5 include/hw/or-irq.h: Add missing include guard
c84bfdeac7 hw/misc/unimp: Move struct to header file
0eef77da17 target/arm: Add Cortex-M33
6bc121a492 armv7m: Forward init-svtor property to CPU object
06b6e8cd1f target/arm: Define init-svtor property for the reset secure VTOR 
value
856e5cff56 armv7m: Forward idau property to CPU object
a0d1e1c86d target/arm: Define an IDAU interface
c33cc72800 hw/arm/armv7m: Honour CPU's address space for image loads
bca17d128e hw/arm/boot: Honour CPU's address space for image loads
a5069eedc1 loader: Add new load_ramdisk_as()

=== OUTPUT BEGIN ===
Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc'
Cloning into '/var/tmp/patchew-tester-tmp-e9pukhul/src/dtc'...
Submodule path 'dtc': checked out 'e54388015af1fb4bf04d0bca99caba1074d9cc42'
  BUILD   centos6
make[1]: Entering directory '/var/tmp/patchew-tester-tmp-e9pukhul/src'
  GEN 
/var/tmp/patchew-tester-tmp-e9pukhul/src/docker-src.2018-02-24-01.10.28.9237/qemu.tar
Cloning into 
'/var/tmp/patchew-tester-tmp-e9pukhul/src/docker-src.2018-02-24-01.10.28.9237/qemu.tar.vroot'...
done.
Your branch is up-to-date with 'origin/test'.
Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc'
Cloning into 
'/var/tmp/patchew-tester-tmp-e9pukhul/src/docker-src.2018-02-24-01.10.28.9237/qemu.tar.vroot/dtc'...
Submodule path 'dtc': checked out 'e54388015af1fb4bf04d0bca99caba1074d9cc42'
Submodule 'ui/keycodemapdb' (git://git.qemu.org/keycodemapdb.git) registered 
for path 'ui/keycodemapdb'
Cloning into 
'/var/tmp/patchew-tester-tmp-e9pukhul/src/docker-src.2018-02-24-01.10.28.9237/qemu.tar.vroot/ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out 
'6b3d716e2b6472eb7189d3220552280ef3d832ce'
  COPYRUNNER
RUN test-quick in qemu:centos6 
Packages installed:
SDL-devel-1.2.14-7.el6_7.1.x86_64
bison-2.4.1-5.el6.x86_64
bzip2-devel-1.0.5-7.el6_0.x86_64
ccache-3.1.6-2.el6.x86_64
csnappy-devel-0-6.20150729gitd7bc683.el6.x86_64
flex-2.5.35-9.el6.x86_64
gcc-4.4.7-18.el6.x86_64
gettext-0.17-18.el6.x86_64
git-1.7.1-9.el6_9.x86_64
glib2-devel-2.28.8-9.el6.x86_64
libepoxy-devel-1.2-3.el6.x86_64
libfdt-devel-1.4.0-1.el6.x86_64
librdmacm-devel-1.0.21-0.el6.x86_64
lzo-devel-2.03-3.1.el6_5.1.x86_64
make-3.81-23.el6.x86_64
mesa-libEGL-devel-11.0.7-4.el6.x86_64
mesa-libgbm-devel-11.0.7-4.el6.x86_64
package g++ is not installed
pixman-devel-0.32.8-1.el6.x86_64
spice-glib-devel-0.26-8.el6.x86_64
spice-server-devel-0.12.4-16.el6.x86_64
tar-1.23-15.el6_8.x86_64
vte-devel-0.25.1-9.el6.x86_64
xen-devel-4.6.6-2.el6.x86_64
zlib-devel-1.2.3-29.el6.x86_64

Environment variables:
PACKAGES=bison bzip2-devel ccache csnappy-devel flex g++
 gcc gettext git glib2-devel libepoxy-devel libfdt-devel
 librdmacm-devel lzo-devel make mesa-libEGL-devel 
mesa-libgbm-devel pixman-devel SDL-devel spice-glib-devel 
spice-server-devel tar vte-devel xen-devel zlib-devel
HOSTNAME=c9a30019043f
MAKEFLAGS= -j8
J=8
CCACHE_DIR=/var/tmp/ccache
EXTRA_CONFIGURE_OPTS=
V=
SHOW_ENV=1
PATH=/usr/lib/ccache:/usr/lib64/ccache:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
PWD=/
TARGET_LIST=
SHLVL=1
HOME=/root
TEST_DIR=/tmp/qemu-test
FEATURES= dtc
DEBUG=
_=/usr/bin/env

Configure options:
--enable-werror --target-list=x86_64-softmmu,aarch64-softmmu 
--prefix=/tmp/qemu-test/install
No C++ compiler available; disabling C++ specific optional code
Install prefix/tmp/qemu-test/install
BIOS directory/tmp/qemu-test/install/share/qemu
firmware path /tmp/qemu-test/install/share/qemu-firmware
binary directory  /tmp/qemu-test/install/bin
library directory /tmp/qemu-test/install/lib
module directory  /tmp/qemu-test/install

Re: [Qemu-devel] [PATCH 00/19] Add Cortex-M33 and mps2-an505 board model

[Eric Blake]

On 02/22/2018 01:11 PM, Peter Maydell wrote:


ERROR: line over 90 characters
#54: FILE: hw/arm/mps2-tz.c:21:
+ * 
https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2




Does anybody better with perl and more familiar with checkpatch's
internals feel like tweaking it to suppress the over-long-line
complaint for URLs ?


This one-liner appears to do the trick; I'll submit it formally in 
another thread:


diff --git i/scripts/checkpatch.pl w/scripts/checkpatch.pl
index 1b4b812e28f..0d3f753c665 100755
--- i/scripts/checkpatch.pl
+++ w/scripts/checkpatch.pl
@@ -1447,9 +1447,10 @@ sub process {
 # check we are in a valid source file if not then ignore this hunk
next if ($realfile !~ /$SrcFile/);

-#90 column limit
+#90 column limit; exempt URLs, if no other words on line
if ($line =~ /^\+/ &&
!($line =~ /^\+\s*"[^"]*"\s*(?:\s*|,|\)\s*;)\s*$/) &&
+   !($rawline =~ /^[^[:alnum:]]*https?:\S*$/) &&
$length > 80)
{
if ($length > 90) {


--
Eric Blake, Principal Software Engineer
Red Hat, Inc.   +1-919-301-3266
Virtualization:  qemu.org | libvirt.org

Re: [Qemu-devel] [PATCH 00/19] Add Cortex-M33 and mps2-an505 board model

[Peter Maydell]

On 22 February 2018 at 19:03,   wrote:

> WARNING: line over 80 characters
> #530: FILE: include/hw/misc/iotkit-secctl.h:14:
> + * 
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html

> WARNING: line over 80 characters
> #660: FILE: include/hw/arm/iotkit.h:13:
> + * 
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html

> ERROR: line over 90 characters
> #54: FILE: hw/arm/mps2-tz.c:21:
> + * 
> https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2
>
> ERROR: line over 90 characters
> #57: FILE: hw/arm/mps2-tz.c:24:
> + * 
> http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf
>
> WARNING: line over 80 characters
> #63: FILE: hw/arm/mps2-tz.c:30:
> + *   
> http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html

Does anybody better with perl and more familiar with checkpatch's
internals feel like tweaking it to suppress the over-long-line
complaint for URLs ?

thanks
-- PMM

Re: [Qemu-devel] [PATCH 00/19] Add Cortex-M33 and mps2-an505 board model

[no-reply]

Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20180220180325.29818-1-peter.mayd...@linaro.org
Subject: [Qemu-devel] [PATCH 00/19] Add Cortex-M33 and mps2-an505 board model

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
e180eb0b18 mps2-an505: New board model: MPS2 with AN505 Cortex-M33 FPGA image
e9d9691d66 hw/arm/iotkit: Model Arm IOT Kit
71a5d961f5 hw/misc/iotkit-secctl: Add remaining simple registers
4343d21683 hw/misc/iotkit-secctl: Add handling for PPCs
59b4605d5b hw/misc/iotkit-secctl: Arm IoT Kit security controller initial 
skeleton
73cfb2ca15 hw/misc/tz-ppc: Model TrustZone peripheral protection controller
36338baf4d hw/misc/mps2-fpgaio: FPGA control block for MPS2 AN505
b5a8b9e25d hw/core/split-irq: Device that splits IRQ lines
e28c0c384a qdev: Add new qdev_init_gpio_in_named_with_opaque()
92a11b2fb0 include/hw/or-irq.h: Add missing include guard
861290d23d hw/misc/unimp: Move struct to header file
cdd841df46 target/arm: Add Cortex-M33
94ad7cd114 armv7m: Forward init-svtor property to CPU object
f5c67afec5 target/arm: Define init-svtor property for the reset secure VTOR 
value
1e54044ac4 armv7m: Forward idau property to CPU object
8d2edaf899 target/arm: Define an IDAU interface
3a8d8926c5 hw/arm/armv7m: Honour CPU's address space for image loads
2a05095d98 hw/arm/boot: Honour CPU's address space for image loads
e365ccf88b loader: Add new load_ramdisk_as()

=== OUTPUT BEGIN ===
Checking PATCH 1/19: loader: Add new load_ramdisk_as()...
Checking PATCH 2/19: hw/arm/boot: Honour CPU's address space for image loads...
Checking PATCH 3/19: hw/arm/armv7m: Honour CPU's address space for image 
loads...
Checking PATCH 4/19: target/arm: Define an IDAU interface...
Checking PATCH 5/19: armv7m: Forward idau property to CPU object...
Checking PATCH 6/19: target/arm: Define init-svtor property for the reset 
secure VTOR value...
Checking PATCH 7/19: armv7m: Forward init-svtor property to CPU object...
Checking PATCH 8/19: target/arm: Add Cortex-M33...
Checking PATCH 9/19: hw/misc/unimp: Move struct to header file...
Checking PATCH 10/19: include/hw/or-irq.h: Add missing include guard...
Checking PATCH 11/19: qdev: Add new qdev_init_gpio_in_named_with_opaque()...
Checking PATCH 12/19: hw/core/split-irq: Device that splits IRQ lines...
Checking PATCH 13/19: hw/misc/mps2-fpgaio: FPGA control block for MPS2 AN505...
Checking PATCH 14/19: hw/misc/tz-ppc: Model TrustZone peripheral protection 
controller...
Checking PATCH 15/19: hw/misc/iotkit-secctl: Arm IoT Kit security controller 
initial skeleton...
WARNING: line over 80 characters
#530: FILE: include/hw/misc/iotkit-secctl.h:14:
+ * 
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html

total: 0 errors, 1 warnings, 513 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 16/19: hw/misc/iotkit-secctl: Add handling for PPCs...
Checking PATCH 17/19: hw/misc/iotkit-secctl: Add remaining simple registers...
Checking PATCH 18/19: hw/arm/iotkit: Model Arm IOT Kit...
WARNING: line over 80 characters
#660: FILE: include/hw/arm/iotkit.h:13:
+ * 
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html

total: 0 errors, 1 warnings, 718 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 19/19: mps2-an505: New board model: MPS2 with AN505 Cortex-M33 
FPGA image...
ERROR: line over 90 characters
#54: FILE: hw/arm/mps2-tz.c:21:
+ * 
https://developer.arm.com/products/system-design/development-boards/fpga-prototyping-boards/mps2

ERROR: line over 90 characters
#57: FILE: hw/arm/mps2-tz.c:24:
+ * 
http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf

WARNING: line over 80 characters
#63: FILE: hw/arm/mps2-tz.c:30:
+ *   
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html

total: 2 errors, 1 warnings, 510 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECK

[Qemu-devel] [PATCH 00/19] Add Cortex-M33 and mps2-an505 board model

[Peter Maydell]

This patchset enables the Cortex-M33 v8M CPU type and adds a board model
for it: the AN505 FPGA image for the MPS2+ devboard. The AN505 uses and
extends the "IoT Kit", which is a reference subsystem that includes the
CPU and some devices, and is intended to be extended further to build
a complete device. Both the IoT Kit and the FPGA use devices documented
in the ARM CoreLink SIE-200 System IP for Embedded TRM.

Useful documents (these are also linked in comments in the relevant
source files):

Board TRM:
 
http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_06_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_06_en.pdf
Application Note AN505 (documenting the FPGA image):
 http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html
ARMv8M IoT Kit FVP User Guide (ARM ECM0601256):
 
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
ARM CoreLink SIE-200 System IP for Embedded TRM (DDI 0571G):
https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g

The most complicated thing here is the various kinds of security
controller in the system, so here's a summary of them which will
hopefully make the patchset easier to navigate:

 * Secure Attribution Unit (SAU) -- this is part of the CPU. Rather like
   the MPU, it provides registers that the guest can use to specify the
   security attributes for memory regions. The QEMU implementation is
   already in master. If the SAU says 'no' then a SecureFault exception
   is taken.
 * Implementation Defined Attribution Unit (IDAU) -- an implementation
   defined mechanism for an SoC to specify security attributes for memory.
   In Cortex-M33 hardware, the CPU puts the address of each memory access
   out on a special set of signal lines, and the SoC then has to respond
   with its attribute information for that address. Typically this is set
   up to be simple combinatorial logic; for this board, for instance the
   IDAU reports the inverse of address bit 28 as the NS attribute, creating
   a series of 256MB regions NS/S/NS/S... over the whole address space.
   If the IDAU attributes are more restrictive than the SAU then the IDAU
   overrides the SAU settings. Again, transgressions get a SecureFault.
   In QEMU we define a QOM interface for the IDAU which can then be
   implemented by the SoC or board class. In this series patch 4 has
   the interface definition and the CPU use of it; patch 18 has the
   SoC implementation of its end.
 * The Peripheral Protection Controller (PPC) is part of the interconnect
   fabric outside the CPU. It sits in front of non-TrustZone aware devices
   and can configurably block attempts to access them from the wrong
   security state or privilege mode. Blocked transactions can be configured
   to either cause a bus error, or to be RAZ/WI. The PPC has no register
   interface of its own, but is configured by setting signal lines into it.
   It's one of the devices in the SIE-200 TRM.
 * The Memory Protection Controller (MPC) is similar in purpose to the PPC
   but specifically for sitting in front of RAM. It allows more granular
   configuration of protection so that one RAM can be split between Secure
   and Nonsecure. The IoTKit and FPGA should have MPCs, but I have not
   implemented them in this patchset (it seemed big enough as it is :-))
   It's also documented in the SIE-200 TRM.
 * The Master Security Controller (MSC) sits in front of the transaction
   master interface of a non-trustzone-aware device that can initiate
   memory transactions (DMA controllers, for instance). It allows
   transactions made by the device to be configurably blocked, so that a
   DMA controller can be given to the non-secure world but prevented from
   making accesses to secure-only memory. Like the PPC, it has no register
   interface and is configured using signal lines. It's documented in the
   SIE-200 TRM. I haven't implemented the MSC in this patchset.
 * The IoT Kit security controller is an ad-hoc collection of registers
   that let the guest configure various bits of the IoT Kit subsystem.
   It includes registers that control both the 2 PPCs in the IoT Kit and
   the 5 PPCs in the FPGA, and also registers to control the MSCs. The
   QEMU implementation is in patches 15-17 (and used in subsequent patches).

Patch series structure:

Patches 1..3 make the Arm -kernel loading code honour the CPU's
AddressSpace -- this is necessary for this board because most of the
devices and RAM don't live in address_space_system(). They've already
been on-list and reviewed; included here to make the series
self-contained.

Patches 4 and 5 are the CPU end of the IDAU.

Patches 6 and 7 allow the board/SoC code to specify the reset value of
the secure Vector Table Offset Register. This is configurable for
Cortex-M33 hardware, and on this board it's not zero.

Patch 8 adds the CPU definition for the Cortex-M33, since we now have
all the