Re: [Qemu-devel] [PATCH 03/11] apb: rename APB functions to use sabre prefix

[Philippe Mathieu-Daudé]

On 01/14/2018 07:47 AM, Mark Cave-Ayland wrote:
> As hinted in the comment at the top of the file, the naming convention for the
> APB types/QOM functions isn't correct. As a starting point we can at least
> rename the APB type and related functions to improve the readability of apb.c.

comment you remove later, ok.

> 
> Signed-off-by: Mark Cave-Ayland 

Reviewed-by: Philippe Mathieu-Daudé 

> ---
>  hw/pci-host/apb.c | 109 
> +++---
>  include/hw/pci-host/apb.h |   1 -
>  2 files changed, 54 insertions(+), 56 deletions(-)
> 
> diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
> index 43ee42d170..d5c459a2df 100644
> --- a/hw/pci-host/apb.c
> +++ b/hw/pci-host/apb.c
> @@ -70,7 +70,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
>  
>  #define NO_IRQ_REQUEST (MAX_IVEC + 1)
>  
> -static inline void pbm_set_request(APBState *s, unsigned int irq_num)
> +static inline void sabre_set_request(APBState *s, unsigned int irq_num)
>  {
>  APB_DPRINTF("%s: request irq %d\n", __func__, irq_num);
>  
> @@ -78,14 +78,13 @@ static inline void pbm_set_request(APBState *s, unsigned 
> int irq_num)
>  qemu_set_irq(s->ivec_irqs[irq_num], 1);
>  }
>  
> -static inline void pbm_check_irqs(APBState *s)
> +static inline void sabre_check_irqs(APBState *s)
>  {
> -
>  unsigned int i;
>  
>  /* Previous request is not acknowledged, resubmit */
>  if (s->irq_request != NO_IRQ_REQUEST) {
> -pbm_set_request(s, s->irq_request);
> +sabre_set_request(s, s->irq_request);
>  return;
>  }
>  /* no request pending */
> @@ -95,7 +94,7 @@ static inline void pbm_check_irqs(APBState *s)
>  for (i = 0; i < 32; i++) {
>  if (s->pci_irq_in & (1ULL << i)) {
>  if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) {
> -pbm_set_request(s, i);
> +sabre_set_request(s, i);
>  return;
>  }
>  }
> @@ -103,28 +102,28 @@ static inline void pbm_check_irqs(APBState *s)
>  for (i = 32; i < 64; i++) {
>  if (s->pci_irq_in & (1ULL << i)) {
>  if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) {
> -pbm_set_request(s, i);
> +sabre_set_request(s, i);
>  break;
>  }
>  }
>  }
>  }
>  
> -static inline void pbm_clear_request(APBState *s, unsigned int irq_num)
> +static inline void sabre_clear_request(APBState *s, unsigned int irq_num)
>  {
>  APB_DPRINTF("%s: clear request irq %d\n", __func__, irq_num);
>  qemu_set_irq(s->ivec_irqs[irq_num], 0);
>  s->irq_request = NO_IRQ_REQUEST;
>  }
>  
> -static AddressSpace *pbm_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
> +static AddressSpace *sabre_pci_dma_iommu(PCIBus *bus, void *opaque, int 
> devfn)
>  {
>  IOMMUState *is = opaque;
>  
>  return >iommu_as;
>  }
>  
> -static void apb_config_writel (void *opaque, hwaddr addr,
> +static void sabre_config_write(void *opaque, hwaddr addr,
> uint64_t val, unsigned size)
>  {
>  APBState *s = opaque;
> @@ -141,9 +140,9 @@ static void apb_config_writel (void *opaque, hwaddr addr,
>  s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK;
>  s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
>  if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) {
> -pbm_clear_request(s, ino);
> +sabre_clear_request(s, ino);
>  }
> -pbm_check_irqs(s);
> +sabre_check_irqs(s);
>  }
>  break;
>  case 0x1000 ... 0x107f: /* OBIO interrupt control */
> @@ -153,17 +152,17 @@ static void apb_config_writel (void *opaque, hwaddr 
> addr,
>  s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
>  if ((s->irq_request == (ino | 0x20))
>   && !(val & ~PBM_PCI_IMR_MASK)) {
> -pbm_clear_request(s, ino | 0x20);
> +sabre_clear_request(s, ino | 0x20);
>  }
> -pbm_check_irqs(s);
> +sabre_check_irqs(s);
>  }
>  break;
>  case 0x1400 ... 0x14ff: /* PCI interrupt clear */
>  if (addr & 4) {
>  unsigned int ino = (addr & 0xff) >> 5;
>  if ((s->irq_request / 4)  == ino) {
> -pbm_clear_request(s, s->irq_request);
> -pbm_check_irqs(s);
> +sabre_clear_request(s, s->irq_request);
> +sabre_check_irqs(s);
>  }
>  }
>  break;
> @@ -171,8 +170,8 @@ static void apb_config_writel (void *opaque, hwaddr addr,
>  if (addr & 4) {
>  unsigned int ino = ((addr & 0xff) >> 3) | 0x20;
>  if (s->irq_request == ino) {
> -pbm_clear_request(s, ino);
> -pbm_check_irqs(s);
> +sabre_clear_request(s, ino);
> +  

[Qemu-devel] [PATCH 03/11] apb: rename APB functions to use sabre prefix

[Mark Cave-Ayland]

As hinted in the comment at the top of the file, the naming convention for the
APB types/QOM functions isn't correct. As a starting point we can at least
rename the APB type and related functions to improve the readability of apb.c.

Signed-off-by: Mark Cave-Ayland 
---
 hw/pci-host/apb.c | 109 +++---
 include/hw/pci-host/apb.h |   1 -
 2 files changed, 54 insertions(+), 56 deletions(-)

diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c
index 43ee42d170..d5c459a2df 100644
--- a/hw/pci-host/apb.c
+++ b/hw/pci-host/apb.c
@@ -70,7 +70,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
 
 #define NO_IRQ_REQUEST (MAX_IVEC + 1)
 
-static inline void pbm_set_request(APBState *s, unsigned int irq_num)
+static inline void sabre_set_request(APBState *s, unsigned int irq_num)
 {
 APB_DPRINTF("%s: request irq %d\n", __func__, irq_num);
 
@@ -78,14 +78,13 @@ static inline void pbm_set_request(APBState *s, unsigned 
int irq_num)
 qemu_set_irq(s->ivec_irqs[irq_num], 1);
 }
 
-static inline void pbm_check_irqs(APBState *s)
+static inline void sabre_check_irqs(APBState *s)
 {
-
 unsigned int i;
 
 /* Previous request is not acknowledged, resubmit */
 if (s->irq_request != NO_IRQ_REQUEST) {
-pbm_set_request(s, s->irq_request);
+sabre_set_request(s, s->irq_request);
 return;
 }
 /* no request pending */
@@ -95,7 +94,7 @@ static inline void pbm_check_irqs(APBState *s)
 for (i = 0; i < 32; i++) {
 if (s->pci_irq_in & (1ULL << i)) {
 if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) {
-pbm_set_request(s, i);
+sabre_set_request(s, i);
 return;
 }
 }
@@ -103,28 +102,28 @@ static inline void pbm_check_irqs(APBState *s)
 for (i = 32; i < 64; i++) {
 if (s->pci_irq_in & (1ULL << i)) {
 if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) {
-pbm_set_request(s, i);
+sabre_set_request(s, i);
 break;
 }
 }
 }
 }
 
-static inline void pbm_clear_request(APBState *s, unsigned int irq_num)
+static inline void sabre_clear_request(APBState *s, unsigned int irq_num)
 {
 APB_DPRINTF("%s: clear request irq %d\n", __func__, irq_num);
 qemu_set_irq(s->ivec_irqs[irq_num], 0);
 s->irq_request = NO_IRQ_REQUEST;
 }
 
-static AddressSpace *pbm_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
+static AddressSpace *sabre_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn)
 {
 IOMMUState *is = opaque;
 
 return >iommu_as;
 }
 
-static void apb_config_writel (void *opaque, hwaddr addr,
+static void sabre_config_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
 {
 APBState *s = opaque;
@@ -141,9 +140,9 @@ static void apb_config_writel (void *opaque, hwaddr addr,
 s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK;
 s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
 if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) {
-pbm_clear_request(s, ino);
+sabre_clear_request(s, ino);
 }
-pbm_check_irqs(s);
+sabre_check_irqs(s);
 }
 break;
 case 0x1000 ... 0x107f: /* OBIO interrupt control */
@@ -153,17 +152,17 @@ static void apb_config_writel (void *opaque, hwaddr addr,
 s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK;
 if ((s->irq_request == (ino | 0x20))
  && !(val & ~PBM_PCI_IMR_MASK)) {
-pbm_clear_request(s, ino | 0x20);
+sabre_clear_request(s, ino | 0x20);
 }
-pbm_check_irqs(s);
+sabre_check_irqs(s);
 }
 break;
 case 0x1400 ... 0x14ff: /* PCI interrupt clear */
 if (addr & 4) {
 unsigned int ino = (addr & 0xff) >> 5;
 if ((s->irq_request / 4)  == ino) {
-pbm_clear_request(s, s->irq_request);
-pbm_check_irqs(s);
+sabre_clear_request(s, s->irq_request);
+sabre_check_irqs(s);
 }
 }
 break;
@@ -171,8 +170,8 @@ static void apb_config_writel (void *opaque, hwaddr addr,
 if (addr & 4) {
 unsigned int ino = ((addr & 0xff) >> 3) | 0x20;
 if (s->irq_request == ino) {
-pbm_clear_request(s, ino);
-pbm_check_irqs(s);
+sabre_clear_request(s, ino);
+sabre_check_irqs(s);
 }
 }
 break;
@@ -202,7 +201,7 @@ static void apb_config_writel (void *opaque, hwaddr addr,
 }
 }
 
-static uint64_t apb_config_readl (void *opaque,
+static uint64_t sabre_config_read(void *opaque,
   hwaddr addr, unsigned size)
 {
 APBState *s = opaque;
@@ -258,14 +257,14 @@ static uint64_t