[Qemu-devel] [PATCH 05/15] pci-host: Delegate bswap to mmio layer
The only reason we have bswap versions of the pci host code is that
most pci host devices are little endian. The ppc e500 is the only
odd one here, being big endian.
So let's directly pass the endianness down to the mmio layer and not
worry about it on the pci host layer.
Signed-off-by: Alexander Graf
---
hw/dec_pci.c |6 ++-
hw/grackle_pci.c |6 ++-
hw/pci_host.c| 105 ++---
hw/pci_host.h|6 +--
hw/ppce500_pci.c |6 ++-
hw/unin_pci.c| 18 ++---
6 files changed, 46 insertions(+), 101 deletions(-)
diff --git a/hw/dec_pci.c b/hw/dec_pci.c
index aa07ab7..bf88f2a 100644
--- a/hw/dec_pci.c
+++ b/hw/dec_pci.c
@@ -96,8 +96,10 @@ static int pci_dec_21154_init_device(SysBusDevice *dev)
s = FROM_SYSBUS(DECState, dev);
-pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
-pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
+pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
+ DEVICE_LITTLE_ENDIAN);
+pci_mem_data = pci_host_data_register_mmio(&s->host_state,
+ DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
return 0;
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
index 91c755f..bd3d6b0 100644
--- a/hw/grackle_pci.c
+++ b/hw/grackle_pci.c
@@ -108,8 +108,10 @@ static int pci_grackle_init_device(SysBusDevice *dev)
s = FROM_SYSBUS(GrackleState, dev);
-pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
-pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
+pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
+ DEVICE_LITTLE_ENDIAN);
+pci_mem_data = pci_host_data_register_mmio(&s->host_state,
+ DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
diff --git a/hw/pci_host.c b/hw/pci_host.c
index a6e39c9..eebff7a 100644
--- a/hw/pci_host.c
+++ b/hw/pci_host.c
@@ -78,64 +78,39 @@ uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
return val;
}
-static void pci_host_config_write_swap(ReadWriteHandler *handler,
- pcibus_t addr, uint32_t val, int len)
+static void pci_host_config_write(ReadWriteHandler *handler,
+ pcibus_t addr, uint32_t val, int len)
{
PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
PCI_DPRINTF("%s addr %" FMT_PCIBUS " %d val %"PRIx32"\n",
__func__, addr, len, val);
-val = qemu_bswap_len(val, len);
s->config_reg = val;
}
-static uint32_t pci_host_config_read_swap(ReadWriteHandler *handler,
- pcibus_t addr, int len)
+static uint32_t pci_host_config_read(ReadWriteHandler *handler,
+ pcibus_t addr, int len)
{
PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
uint32_t val = s->config_reg;
-val = qemu_bswap_len(val, len);
PCI_DPRINTF("%s addr %" FMT_PCIBUS " len %d val %"PRIx32"\n",
__func__, addr, len, val);
return val;
}
-static void pci_host_config_write_noswap(ReadWriteHandler *handler,
- pcibus_t addr, uint32_t val, int len)
-{
-PCIHostState *s = container_of(handler, PCIHostState, conf_noswap_handler);
-
-PCI_DPRINTF("%s addr %" FMT_PCIBUS " %d val %"PRIx32"\n",
-__func__, addr, len, val);
-s->config_reg = val;
-}
-
-static uint32_t pci_host_config_read_noswap(ReadWriteHandler *handler,
-pcibus_t addr, int len)
-{
-PCIHostState *s = container_of(handler, PCIHostState, conf_noswap_handler);
-uint32_t val = s->config_reg;
-
-PCI_DPRINTF("%s addr %" FMT_PCIBUS " len %d val %"PRIx32"\n",
-__func__, addr, len, val);
-return val;
-}
-
-static void pci_host_data_write_swap(ReadWriteHandler *handler,
- pcibus_t addr, uint32_t val, int len)
+static void pci_host_data_write(ReadWriteHandler *handler,
+pcibus_t addr, uint32_t val, int len)
{
PCIHostState *s = container_of(handler, PCIHostState, data_handler);
-
-val = qemu_bswap_len(val, len);
PCI_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n",
addr, len, val);
if (s->config_reg & (1u << 31))
pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
}
-static uint32_t pci_host_data_read_swap(ReadWriteHandler *handler,
-pcibus_t addr, int len)
+static uint32_t pci_host_data_read(ReadWriteHandler *handler,
+
[Qemu-devel] [PATCH 05/15] pci-host: Delegate bswap to mmio layer
The only reason we have bswap versions of the pci host code is that
most pci host devices are little endian. The ppc e500 is the only
odd one here, being big endian.
So let's directly pass the endianness down to the mmio layer and not
worry about it on the pci host layer.
Signed-off-by: Alexander Graf
---
hw/dec_pci.c |6 ++-
hw/grackle_pci.c |6 ++-
hw/pci_host.c| 105 ++---
hw/pci_host.h|6 +--
hw/ppce500_pci.c |6 ++-
hw/unin_pci.c| 18 ++---
6 files changed, 46 insertions(+), 101 deletions(-)
diff --git a/hw/dec_pci.c b/hw/dec_pci.c
index aa07ab7..bf88f2a 100644
--- a/hw/dec_pci.c
+++ b/hw/dec_pci.c
@@ -96,8 +96,10 @@ static int pci_dec_21154_init_device(SysBusDevice *dev)
s = FROM_SYSBUS(DECState, dev);
-pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
-pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
+pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
+ DEVICE_LITTLE_ENDIAN);
+pci_mem_data = pci_host_data_register_mmio(&s->host_state,
+ DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
return 0;
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
index 91c755f..bd3d6b0 100644
--- a/hw/grackle_pci.c
+++ b/hw/grackle_pci.c
@@ -108,8 +108,10 @@ static int pci_grackle_init_device(SysBusDevice *dev)
s = FROM_SYSBUS(GrackleState, dev);
-pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
-pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
+pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
+ DEVICE_LITTLE_ENDIAN);
+pci_mem_data = pci_host_data_register_mmio(&s->host_state,
+ DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
diff --git a/hw/pci_host.c b/hw/pci_host.c
index a6e39c9..eebff7a 100644
--- a/hw/pci_host.c
+++ b/hw/pci_host.c
@@ -78,64 +78,39 @@ uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
return val;
}
-static void pci_host_config_write_swap(ReadWriteHandler *handler,
- pcibus_t addr, uint32_t val, int len)
+static void pci_host_config_write(ReadWriteHandler *handler,
+ pcibus_t addr, uint32_t val, int len)
{
PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
PCI_DPRINTF("%s addr %" FMT_PCIBUS " %d val %"PRIx32"\n",
__func__, addr, len, val);
-val = qemu_bswap_len(val, len);
s->config_reg = val;
}
-static uint32_t pci_host_config_read_swap(ReadWriteHandler *handler,
- pcibus_t addr, int len)
+static uint32_t pci_host_config_read(ReadWriteHandler *handler,
+ pcibus_t addr, int len)
{
PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
uint32_t val = s->config_reg;
-val = qemu_bswap_len(val, len);
PCI_DPRINTF("%s addr %" FMT_PCIBUS " len %d val %"PRIx32"\n",
__func__, addr, len, val);
return val;
}
-static void pci_host_config_write_noswap(ReadWriteHandler *handler,
- pcibus_t addr, uint32_t val, int len)
-{
-PCIHostState *s = container_of(handler, PCIHostState, conf_noswap_handler);
-
-PCI_DPRINTF("%s addr %" FMT_PCIBUS " %d val %"PRIx32"\n",
-__func__, addr, len, val);
-s->config_reg = val;
-}
-
-static uint32_t pci_host_config_read_noswap(ReadWriteHandler *handler,
-pcibus_t addr, int len)
-{
-PCIHostState *s = container_of(handler, PCIHostState, conf_noswap_handler);
-uint32_t val = s->config_reg;
-
-PCI_DPRINTF("%s addr %" FMT_PCIBUS " len %d val %"PRIx32"\n",
-__func__, addr, len, val);
-return val;
-}
-
-static void pci_host_data_write_swap(ReadWriteHandler *handler,
- pcibus_t addr, uint32_t val, int len)
+static void pci_host_data_write(ReadWriteHandler *handler,
+pcibus_t addr, uint32_t val, int len)
{
PCIHostState *s = container_of(handler, PCIHostState, data_handler);
-
-val = qemu_bswap_len(val, len);
PCI_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n",
addr, len, val);
if (s->config_reg & (1u << 31))
pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
}
-static uint32_t pci_host_data_read_swap(ReadWriteHandler *handler,
-pcibus_t addr, int len)
+static uint32_t pci_host_data_read(ReadWriteHandler *handler,
+
[Qemu-devel] [PATCH 05/15] pci-host: Delegate bswap to mmio layer
The only reason we have bswap versions of the pci host code is that
most pci host devices are little endian. The ppc e500 is the only
odd one here, being big endian.
So let's directly pass the endianness down to the mmio layer and not
worry about it on the pci host layer.
Signed-off-by: Alexander Graf
---
hw/dec_pci.c |6 ++-
hw/grackle_pci.c |6 ++-
hw/pci_host.c| 105 ++---
hw/pci_host.h|6 +--
hw/ppce500_pci.c |6 ++-
hw/unin_pci.c| 18 ++---
6 files changed, 46 insertions(+), 101 deletions(-)
diff --git a/hw/dec_pci.c b/hw/dec_pci.c
index aa07ab7..bf88f2a 100644
--- a/hw/dec_pci.c
+++ b/hw/dec_pci.c
@@ -96,8 +96,10 @@ static int pci_dec_21154_init_device(SysBusDevice *dev)
s = FROM_SYSBUS(DECState, dev);
-pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
-pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
+pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
+ DEVICE_LITTLE_ENDIAN);
+pci_mem_data = pci_host_data_register_mmio(&s->host_state,
+ DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
return 0;
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
index 91c755f..bd3d6b0 100644
--- a/hw/grackle_pci.c
+++ b/hw/grackle_pci.c
@@ -108,8 +108,10 @@ static int pci_grackle_init_device(SysBusDevice *dev)
s = FROM_SYSBUS(GrackleState, dev);
-pci_mem_config = pci_host_conf_register_mmio(&s->host_state, 1);
-pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
+pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
+ DEVICE_LITTLE_ENDIAN);
+pci_mem_data = pci_host_data_register_mmio(&s->host_state,
+ DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
diff --git a/hw/pci_host.c b/hw/pci_host.c
index a6e39c9..eebff7a 100644
--- a/hw/pci_host.c
+++ b/hw/pci_host.c
@@ -78,64 +78,39 @@ uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
return val;
}
-static void pci_host_config_write_swap(ReadWriteHandler *handler,
- pcibus_t addr, uint32_t val, int len)
+static void pci_host_config_write(ReadWriteHandler *handler,
+ pcibus_t addr, uint32_t val, int len)
{
PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
PCI_DPRINTF("%s addr %" FMT_PCIBUS " %d val %"PRIx32"\n",
__func__, addr, len, val);
-val = qemu_bswap_len(val, len);
s->config_reg = val;
}
-static uint32_t pci_host_config_read_swap(ReadWriteHandler *handler,
- pcibus_t addr, int len)
+static uint32_t pci_host_config_read(ReadWriteHandler *handler,
+ pcibus_t addr, int len)
{
PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
uint32_t val = s->config_reg;
-val = qemu_bswap_len(val, len);
PCI_DPRINTF("%s addr %" FMT_PCIBUS " len %d val %"PRIx32"\n",
__func__, addr, len, val);
return val;
}
-static void pci_host_config_write_noswap(ReadWriteHandler *handler,
- pcibus_t addr, uint32_t val, int len)
-{
-PCIHostState *s = container_of(handler, PCIHostState, conf_noswap_handler);
-
-PCI_DPRINTF("%s addr %" FMT_PCIBUS " %d val %"PRIx32"\n",
-__func__, addr, len, val);
-s->config_reg = val;
-}
-
-static uint32_t pci_host_config_read_noswap(ReadWriteHandler *handler,
-pcibus_t addr, int len)
-{
-PCIHostState *s = container_of(handler, PCIHostState, conf_noswap_handler);
-uint32_t val = s->config_reg;
-
-PCI_DPRINTF("%s addr %" FMT_PCIBUS " len %d val %"PRIx32"\n",
-__func__, addr, len, val);
-return val;
-}
-
-static void pci_host_data_write_swap(ReadWriteHandler *handler,
- pcibus_t addr, uint32_t val, int len)
+static void pci_host_data_write(ReadWriteHandler *handler,
+pcibus_t addr, uint32_t val, int len)
{
PCIHostState *s = container_of(handler, PCIHostState, data_handler);
-
-val = qemu_bswap_len(val, len);
PCI_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n",
addr, len, val);
if (s->config_reg & (1u << 31))
pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
}
-static uint32_t pci_host_data_read_swap(ReadWriteHandler *handler,
-pcibus_t addr, int len)
+static uint32_t pci_host_data_read(ReadWriteHandler *handler,
+
