Re: [Qemu-devel] [PATCH 05/24] target-arm: Add exception level to the AArch64 TB flags

2014-01-28 Thread Peter Maydell 
On 28 January 2014 01:28, Peter Crosthwaite
peter.crosthwa...@xilinx.com wrote:
 On Wed, Jan 22, 2014 at 6:12 AM, Peter Maydell peter.mayd...@linaro.org 
 wrote:
 We already implicitly rely on the exception level being
 part of the TB flags for coprocessor access,

 Maybe that's the issue? Why not just treat the exception level as
 state like any other and generate the TCG to just check it at
 execution time?

That would be ferociously expensive, because am I privileged
or not? is baked into every single guest load or store.
Including privilege level in the tb flags is standard for
every target CPU we have.

thanks
-- PMM

Re: [Qemu-devel] [PATCH 05/24] target-arm: Add exception level to the AArch64 TB flags

2014-01-27 Thread Peter Crosthwaite 
On Wed, Jan 22, 2014 at 6:12 AM, Peter Maydell peter.mayd...@linaro.org wrote:
 We already implicitly rely on the exception level being
 part of the TB flags for coprocessor access,

Maybe that's the issue? Why not just treat the exception level as
state like any other and generate the TCG to just check it at
execution time?

Regards,
Peter

 so actually
 include it. (This makes no difference for linux-user mode,
 which is always in EL0, but will be needed for correct
 operation in system emulation.)

 Signed-off-by: Peter Maydell peter.mayd...@linaro.org
 ---
  target-arm/cpu.h | 9 +++--
  1 file changed, 7 insertions(+), 2 deletions(-)

 diff --git a/target-arm/cpu.h b/target-arm/cpu.h
 index 735f385..1aa4495 100644
 --- a/target-arm/cpu.h
 +++ b/target-arm/cpu.h
 @@ -1051,7 +1051,9 @@ static inline int cpu_mmu_index (CPUARMState *env)
  #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
  #define ARM_TBFLAG_BSWAP_CODE_MASK  (1  ARM_TBFLAG_BSWAP_CODE_SHIFT)

 -/* Bit usage when in AArch64 state: currently no bits defined */
 +/* Bit usage when in AArch64 state */
 +#define ARM_TBFLAG_AA64_EL_SHIFT0
 +#define ARM_TBFLAG_AA64_EL_MASK (0x3  ARM_TBFLAG_AA64_EL_SHIFT)

  /* some convenience accessor macros */
  #define ARM_TBFLAG_AARCH64_STATE(F) \
 @@ -1070,13 +1072,16 @@ static inline int cpu_mmu_index (CPUARMState *env)
  (((F)  ARM_TBFLAG_CONDEXEC_MASK)  ARM_TBFLAG_CONDEXEC_SHIFT)
  #define ARM_TBFLAG_BSWAP_CODE(F) \
  (((F)  ARM_TBFLAG_BSWAP_CODE_MASK)  ARM_TBFLAG_BSWAP_CODE_SHIFT)
 +#define ARM_TBFLAG_AA64_EL(F) \
 +(((F)  ARM_TBFLAG_AA64_EL_MASK)  ARM_TBFLAG_AA64_EL_SHIFT)

  static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
  target_ulong *cs_base, int *flags)
  {
  if (is_a64(env)) {
  *pc = env-pc;
 -*flags = ARM_TBFLAG_AARCH64_STATE_MASK;
 +*flags = ARM_TBFLAG_AARCH64_STATE_MASK
 +| arm_current_pl(env)  ARM_TBFLAG_AA64_EL_SHIFT;
  } else {
  int privmode;
  *pc = env-regs[15];
 --
 1.8.5

[Qemu-devel] [PATCH 05/24] target-arm: Add exception level to the AArch64 TB flags

2014-01-21 Thread Peter Maydell 
We already implicitly rely on the exception level being
part of the TB flags for coprocessor access, so actually
include it. (This makes no difference for linux-user mode,
which is always in EL0, but will be needed for correct
operation in system emulation.)

Signed-off-by: Peter Maydell peter.mayd...@linaro.org
---
 target-arm/cpu.h | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 735f385..1aa4495 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1051,7 +1051,9 @@ static inline int cpu_mmu_index (CPUARMState *env)
 #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
 #define ARM_TBFLAG_BSWAP_CODE_MASK  (1  ARM_TBFLAG_BSWAP_CODE_SHIFT)
 
-/* Bit usage when in AArch64 state: currently no bits defined */
+/* Bit usage when in AArch64 state */
+#define ARM_TBFLAG_AA64_EL_SHIFT0
+#define ARM_TBFLAG_AA64_EL_MASK (0x3  ARM_TBFLAG_AA64_EL_SHIFT)
 
 /* some convenience accessor macros */
 #define ARM_TBFLAG_AARCH64_STATE(F) \
@@ -1070,13 +1072,16 @@ static inline int cpu_mmu_index (CPUARMState *env)
 (((F)  ARM_TBFLAG_CONDEXEC_MASK)  ARM_TBFLAG_CONDEXEC_SHIFT)
 #define ARM_TBFLAG_BSWAP_CODE(F) \
 (((F)  ARM_TBFLAG_BSWAP_CODE_MASK)  ARM_TBFLAG_BSWAP_CODE_SHIFT)
+#define ARM_TBFLAG_AA64_EL(F) \
+(((F)  ARM_TBFLAG_AA64_EL_MASK)  ARM_TBFLAG_AA64_EL_SHIFT)
 
 static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
 target_ulong *cs_base, int *flags)
 {
 if (is_a64(env)) {
 *pc = env-pc;
-*flags = ARM_TBFLAG_AARCH64_STATE_MASK;
+*flags = ARM_TBFLAG_AARCH64_STATE_MASK
+| arm_current_pl(env)  ARM_TBFLAG_AA64_EL_SHIFT;
 } else {
 int privmode;
 *pc = env-regs[15];
-- 
1.8.5