Re: [Qemu-devel] [PATCH 07/11] target/sh4: Unify cpu_fregs into FREG

2017-07-05 Thread Philippe Mathieu-Daudé 

On 07/05/2017 09:23 PM, Richard Henderson wrote:

We were treating FREG as an index and REG as a TCGv.
Making FREG return a TCGv is both less confusing and
a step toward cleaner banking of cpu_fregs.

Signed-off-by: Richard Henderson 


Reviewed-by: Philippe Mathieu-Daudé 


---
  target/sh4/translate.c | 123 +
  1 file changed, 52 insertions(+), 71 deletions(-)

diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 20e24d5..e4fd6f2 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -382,10 +382,11 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
  #define REG(x) ctx->gregs[x]
  #define ALTREG(x)  ctx->altregs[x]
  
-#define FREG(x) (ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x))

+#define FREG(x) cpu_fregs[ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x)]
  #define XHACK(x) x) & 1 ) << 4) | ((x) & 0xe))
-#define XREG(x) (ctx->tbflags & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x))
-#define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */
+#define XREG(x) FREG(XHACK(x))
+/* Assumes lsb of (x) is always 0 */
+#define DREG(x) (ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x))
  
  #define CHECK_NOT_DELAY_SLOT \

  if (ctx->envflags & DELAY_SLOT_MASK) {   \
@@ -1005,56 +1006,51 @@ static void _decode_opc(DisasContext * ctx)
CHECK_FPU_ENABLED
  if (ctx->tbflags & FPSCR_SZ) {
TCGv_i64 fp = tcg_temp_new_i64();
-   gen_load_fpr64(fp, XREG(B7_4));
-   gen_store_fpr64(fp, XREG(B11_8));
+   gen_load_fpr64(fp, XHACK(B7_4));
+   gen_store_fpr64(fp, XHACK(B11_8));
tcg_temp_free_i64(fp);
} else {
-   tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
+   tcg_gen_mov_i32(FREG(B11_8), FREG(B7_4));
}
return;
  case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
CHECK_FPU_ENABLED
  if (ctx->tbflags & FPSCR_SZ) {
TCGv addr_hi = tcg_temp_new();
-   int fr = XREG(B7_4);
+   int fr = XHACK(B7_4);
tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
-tcg_gen_qemu_st_i32(cpu_fregs[fr], REG(B11_8),
-ctx->memidx, MO_TEUL);
-tcg_gen_qemu_st_i32(cpu_fregs[fr+1], addr_hi,
-ctx->memidx, MO_TEUL);
+tcg_gen_qemu_st_i32(FREG(fr), REG(B11_8), ctx->memidx, MO_TEUL);
+tcg_gen_qemu_st_i32(FREG(fr + 1), addr_hi, ctx->memidx, MO_TEUL);
tcg_temp_free(addr_hi);
} else {
-tcg_gen_qemu_st_i32(cpu_fregs[FREG(B7_4)], REG(B11_8),
-ctx->memidx, MO_TEUL);
+tcg_gen_qemu_st_i32(FREG(B7_4), REG(B11_8), ctx->memidx, MO_TEUL);
}
return;
  case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
CHECK_FPU_ENABLED
  if (ctx->tbflags & FPSCR_SZ) {
TCGv addr_hi = tcg_temp_new();
-   int fr = XREG(B11_8);
+   int fr = XHACK(B11_8);
tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
-tcg_gen_qemu_ld_i32(cpu_fregs[fr], REG(B7_4), ctx->memidx, 
MO_TEUL);
-tcg_gen_qemu_ld_i32(cpu_fregs[fr+1], addr_hi, ctx->memidx, 
MO_TEUL);
+tcg_gen_qemu_ld_i32(FREG(fr), REG(B7_4), ctx->memidx, MO_TEUL);
+tcg_gen_qemu_ld_i32(FREG(fr + 1), addr_hi, ctx->memidx, MO_TEUL);
tcg_temp_free(addr_hi);
} else {
-tcg_gen_qemu_ld_i32(cpu_fregs[FREG(B11_8)], REG(B7_4),
-ctx->memidx, MO_TEUL);
+tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, MO_TEUL);
}
return;
  case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
CHECK_FPU_ENABLED
  if (ctx->tbflags & FPSCR_SZ) {
TCGv addr_hi = tcg_temp_new();
-   int fr = XREG(B11_8);
+   int fr = XHACK(B11_8);
tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
-tcg_gen_qemu_ld_i32(cpu_fregs[fr], REG(B7_4), ctx->memidx, 
MO_TEUL);
-tcg_gen_qemu_ld_i32(cpu_fregs[fr+1], addr_hi, ctx->memidx, 
MO_TEUL);
+tcg_gen_qemu_ld_i32(FREG(fr), REG(B7_4), ctx->memidx, MO_TEUL);
+tcg_gen_qemu_ld_i32(FREG(fr + 1), addr_hi, ctx->memidx, MO_TEUL);
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8);
tcg_temp_free(addr_hi);
} else {
-tcg_gen_qemu_ld_i32(cpu_fregs[FREG(B11_8)], REG(B7_4),
-ctx->memidx, MO_TEUL);
+tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, MO_TEUL);
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
}
return;
@@ -1063,13 +1059,12 @@ static void _decode_opc(DisasContext * ctx)
  TCGv addr = tcg_temp_new_i32();
  tcg_gen_subi_i32(addr, REG(B11_8), 4);
  if (ctx->tbflags & FPSCR_SZ) {
-   int fr = XREG(B7_4);
-

[Qemu-devel] [PATCH 07/11] target/sh4: Unify cpu_fregs into FREG

2017-07-05 Thread Richard Henderson 
We were treating FREG as an index and REG as a TCGv.
Making FREG return a TCGv is both less confusing and
a step toward cleaner banking of cpu_fregs.

Signed-off-by: Richard Henderson 
---
 target/sh4/translate.c | 123 +
 1 file changed, 52 insertions(+), 71 deletions(-)

diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 20e24d5..e4fd6f2 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -382,10 +382,11 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
 #define REG(x) ctx->gregs[x]
 #define ALTREG(x)  ctx->altregs[x]
 
-#define FREG(x) (ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x))
+#define FREG(x) cpu_fregs[ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x)]
 #define XHACK(x) x) & 1 ) << 4) | ((x) & 0xe))
-#define XREG(x) (ctx->tbflags & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x))
-#define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */
+#define XREG(x) FREG(XHACK(x))
+/* Assumes lsb of (x) is always 0 */
+#define DREG(x) (ctx->tbflags & FPSCR_FR ? (x) ^ 0x10 : (x))
 
 #define CHECK_NOT_DELAY_SLOT \
 if (ctx->envflags & DELAY_SLOT_MASK) {   \
@@ -1005,56 +1006,51 @@ static void _decode_opc(DisasContext * ctx)
CHECK_FPU_ENABLED
 if (ctx->tbflags & FPSCR_SZ) {
TCGv_i64 fp = tcg_temp_new_i64();
-   gen_load_fpr64(fp, XREG(B7_4));
-   gen_store_fpr64(fp, XREG(B11_8));
+   gen_load_fpr64(fp, XHACK(B7_4));
+   gen_store_fpr64(fp, XHACK(B11_8));
tcg_temp_free_i64(fp);
} else {
-   tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]);
+   tcg_gen_mov_i32(FREG(B11_8), FREG(B7_4));
}
return;
 case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */
CHECK_FPU_ENABLED
 if (ctx->tbflags & FPSCR_SZ) {
TCGv addr_hi = tcg_temp_new();
-   int fr = XREG(B7_4);
+   int fr = XHACK(B7_4);
tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
-tcg_gen_qemu_st_i32(cpu_fregs[fr], REG(B11_8),
-ctx->memidx, MO_TEUL);
-tcg_gen_qemu_st_i32(cpu_fregs[fr+1], addr_hi,
-ctx->memidx, MO_TEUL);
+tcg_gen_qemu_st_i32(FREG(fr), REG(B11_8), ctx->memidx, MO_TEUL);
+tcg_gen_qemu_st_i32(FREG(fr + 1), addr_hi, ctx->memidx, MO_TEUL);
tcg_temp_free(addr_hi);
} else {
-tcg_gen_qemu_st_i32(cpu_fregs[FREG(B7_4)], REG(B11_8),
-ctx->memidx, MO_TEUL);
+tcg_gen_qemu_st_i32(FREG(B7_4), REG(B11_8), ctx->memidx, MO_TEUL);
}
return;
 case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
CHECK_FPU_ENABLED
 if (ctx->tbflags & FPSCR_SZ) {
TCGv addr_hi = tcg_temp_new();
-   int fr = XREG(B11_8);
+   int fr = XHACK(B11_8);
tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
-tcg_gen_qemu_ld_i32(cpu_fregs[fr], REG(B7_4), ctx->memidx, 
MO_TEUL);
-tcg_gen_qemu_ld_i32(cpu_fregs[fr+1], addr_hi, ctx->memidx, 
MO_TEUL);
+tcg_gen_qemu_ld_i32(FREG(fr), REG(B7_4), ctx->memidx, MO_TEUL);
+tcg_gen_qemu_ld_i32(FREG(fr + 1), addr_hi, ctx->memidx, MO_TEUL);
tcg_temp_free(addr_hi);
} else {
-tcg_gen_qemu_ld_i32(cpu_fregs[FREG(B11_8)], REG(B7_4),
-ctx->memidx, MO_TEUL);
+tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, MO_TEUL);
}
return;
 case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
CHECK_FPU_ENABLED
 if (ctx->tbflags & FPSCR_SZ) {
TCGv addr_hi = tcg_temp_new();
-   int fr = XREG(B11_8);
+   int fr = XHACK(B11_8);
tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
-tcg_gen_qemu_ld_i32(cpu_fregs[fr], REG(B7_4), ctx->memidx, 
MO_TEUL);
-tcg_gen_qemu_ld_i32(cpu_fregs[fr+1], addr_hi, ctx->memidx, 
MO_TEUL);
+tcg_gen_qemu_ld_i32(FREG(fr), REG(B7_4), ctx->memidx, MO_TEUL);
+tcg_gen_qemu_ld_i32(FREG(fr + 1), addr_hi, ctx->memidx, MO_TEUL);
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8);
tcg_temp_free(addr_hi);
} else {
-tcg_gen_qemu_ld_i32(cpu_fregs[FREG(B11_8)], REG(B7_4),
-ctx->memidx, MO_TEUL);
+tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, MO_TEUL);
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
}
return;
@@ -1063,13 +1059,12 @@ static void _decode_opc(DisasContext * ctx)
 TCGv addr = tcg_temp_new_i32();
 tcg_gen_subi_i32(addr, REG(B11_8), 4);
 if (ctx->tbflags & FPSCR_SZ) {
-   int fr = XREG(B7_4);
-tcg_gen_qemu_st_i32(cpu_fregs[fr+1], addr, ctx->memidx, MO_TEUL);
+   int fr = XHACK(B7_4);
+