Re: [Qemu-devel] [PATCH 09/10] target-avr: updating translate.c to use instructions translation

2016-06-05 Thread Michael Rolnik 
get_opcode no longer present.

I use it for the sake of skip instruction. I do not know a priori the
length of the next instruction as it can be either 16 or 32 bits.

On Sun, Jun 5, 2016 at 6:33 AM, Richard Henderson  wrote:

> On 06/02/2016 01:07 PM, Michael Rolnik wrote:
>
>> +uint32_tget_opcode(
>> +uint8_t const  *code,
>> +unsignedbitBase,
>> +unsignedbitSize)
>> +{
>> +return  *(uint16_t *)code;
>> +}
>>
>
> Unused.  And what was this supposed to do?
>
> +/*  decode next instruction */
>> +ctx.inst[1].cpc = ctx.inst[0].npc;
>> +decode_opc(cpu, , [1]);
>>
>
> Why are you decoding one instruction ahead?
>
> While I can see that this might be keen for some of the skip-next
> instructions, I don't see that you're using that just now.  So perhaps
> delay this until it's actually used?
>
>
> r~
>



-- 
Best Regards,
Michael Rolnik

Re: [Qemu-devel] [PATCH 09/10] target-avr: updating translate.c to use instructions translation

2016-06-04 Thread Richard Henderson 

On 06/02/2016 01:07 PM, Michael Rolnik wrote:

+uint32_tget_opcode(
+uint8_t const  *code,
+unsignedbitBase,
+unsignedbitSize)
+{
+return  *(uint16_t *)code;
+}


Unused.  And what was this supposed to do?


+/*  decode next instruction */
+ctx.inst[1].cpc = ctx.inst[0].npc;
+decode_opc(cpu, , [1]);


Why are you decoding one instruction ahead?

While I can see that this might be keen for some of the skip-next instructions, 
I don't see that you're using that just now.  So perhaps delay this until it's 
actually used?



r~

[Qemu-devel] [PATCH 09/10] target-avr: updating translate.c to use instructions translation

2016-06-02 Thread Michael Rolnik 
Signed-off-by: Michael Rolnik 
---
 target-avr/Makefile.objs |   4 +-
 target-avr/translate.c   | 148 ++-
 2 files changed, 72 insertions(+), 80 deletions(-)

diff --git a/target-avr/Makefile.objs b/target-avr/Makefile.objs
index c503546..8d06d54 100644
--- a/target-avr/Makefile.objs
+++ b/target-avr/Makefile.objs
@@ -1,3 +1,5 @@
-obj-y   += translate.o cpu.o helper.o
+obj-y   += translate.o helper.o cpu.o translate-inst.o
 obj-y   += gdbstub.o
 obj-$(CONFIG_SOFTMMU) += machine.o
+
+obj-y   += decode.o
diff --git a/target-avr/translate.c b/target-avr/translate.c
index e98aaef..0df0184 100644
--- a/target-avr/translate.c
+++ b/target-avr/translate.c
@@ -18,60 +18,31 @@
  *  
  */
 
-#include "qemu/osdep.h"
-
-#include "cpu.h"
-#include "exec/exec-all.h"
-#include "disas/disas.h"
-#include "tcg-op.h"
-#include "exec/cpu_ldst.h"
-
-#include "exec/helper-proto.h"
-#include "exec/helper-gen.h"
-#include "exec/log.h"
-
-typedef struct DisasContext DisasContext;
-typedef struct InstInfo InstInfo;
-
-/*This is the state at translation time.  */
-struct DisasContext {
-struct TranslationBlock*tb;
-
-/*Routine used to access memory */
-int memidx;
-int bstate;
-int singlestep;
-};
-
-enum {
-BS_NONE = 0,/*  Nothing special (none of the below  */
-BS_STOP = 1,/*  We want to stop translation for any reason  */
-BS_BRANCH   = 2,/*  A branch condition is reached   */
-BS_EXCP = 3,/*  An exception condition is reached   */
-};
-
-static TCGv_env cpu_env;
-
-static TCGv cpu_pc;
-
-static TCGv cpu_Cf;
-static TCGv cpu_Zf;
-static TCGv cpu_Nf;
-static TCGv cpu_Vf;
-static TCGv cpu_Sf;
-static TCGv cpu_Hf;
-static TCGv cpu_Tf;
-static TCGv cpu_If;
-
-static TCGv cpu_rampD;
-static TCGv cpu_rampX;
-static TCGv cpu_rampY;
-static TCGv cpu_rampZ;
-
-static TCGv cpu_io[64];
-static TCGv cpu_r[32];
-static TCGv cpu_eind;
-static TCGv cpu_sp;
+#include "translate.h"
+
+
+TCGv_env cpu_env;
+
+TCGv cpu_pc;
+
+TCGv cpu_Cf;
+TCGv cpu_Zf;
+TCGv cpu_Nf;
+TCGv cpu_Vf;
+TCGv cpu_Sf;
+TCGv cpu_Hf;
+TCGv cpu_Tf;
+TCGv cpu_If;
+
+TCGv cpu_rampD;
+TCGv cpu_rampX;
+TCGv cpu_rampY;
+TCGv cpu_rampZ;
+
+TCGv cpu_io[64];
+TCGv cpu_r[32];
+TCGv cpu_eind;
+TCGv cpu_sp;
 
 #include "exec/gen-icount.h"
 #define REG(x)  (cpu_r[x])
@@ -120,30 +91,42 @@ voidavr_translate_init(void)
 done_init = 1;
 }
 
-static inline void  gen_goto_tb(CPUAVRState*env,
-DisasContext   *ctx,
-int n,
-target_ulongdest)
+static void decode_opc(
+AVRCPU *cpu,
+DisasContext   *ctx,
+InstInfo   *inst)
 {
-TranslationBlock   *tb;
+CPUAVRState*env = >env;
 
-tb  = ctx->tb;
+inst->opcode= cpu_ldl_code(env, inst->cpc * 2);   /*  pc points to 
words*/
+inst->length= 16;
+inst->translate = NULL;
 
-if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)
-&&  (ctx->singlestep == 0)) {
-tcg_gen_goto_tb(n);
-tcg_gen_movi_i32(cpu_pc, dest);
-tcg_gen_exit_tb((uintptr_t)tb + n);
-} else {
-tcg_gen_movi_i32(cpu_pc, dest);
+/*  the following function looks onto the opcode as a string of bytes   */
+avr_decode(inst->cpc, >length, inst->opcode, >translate);
 
-if (ctx->singlestep) {
-gen_helper_debug(cpu_env);
-}
-tcg_gen_exit_tb(0);
+if (inst->length == 16) {
+inst->npc= inst->cpc + 1;
+/*  get opcode as 16bit value   */
+inst->opcode = inst->opcode & 0x;
+}
+if (inst->length == 32) {
+inst->npc= inst->cpc + 2;
+/*  get opcode as 32bit value   */
+inst->opcode = (inst->opcode << 16)
+ | (inst->opcode >> 16);
 }
 }
 
+uint32_tget_opcode(
+uint8_t const  *code,
+unsignedbitBase,
+unsignedbitSize)
+{
+return  *(uint16_t *)code;
+}
+
+
 /*generate intermediate code for basic block 'tb'.  */
 voidgen_intermediate_code(
 CPUAVRState*env,
@@ -176,18 +159,21 @@ voidgen_intermediate_code(
 gen_tb_start(tb);
 
 /*  decode first instruction*/
-cpc = pc_start;
-npc = cpc + 1;
+ctx.inst[0].cpc = pc_start;
+decode_opc(cpu, ,

[Qemu-devel] [PATCH 09/10] target-avr: updating translate.c to use instructions translation

2016-06-02 Thread Michael Rolnik 
Signed-off-by: Michael Rolnik 
---
 target-avr/Makefile.objs |   4 +-
 target-avr/translate.c   | 148 ++-
 2 files changed, 72 insertions(+), 80 deletions(-)

diff --git a/target-avr/Makefile.objs b/target-avr/Makefile.objs
index c503546..8d06d54 100644
--- a/target-avr/Makefile.objs
+++ b/target-avr/Makefile.objs
@@ -1,3 +1,5 @@
-obj-y   += translate.o cpu.o helper.o
+obj-y   += translate.o helper.o cpu.o translate-inst.o
 obj-y   += gdbstub.o
 obj-$(CONFIG_SOFTMMU) += machine.o
+
+obj-y   += decode.o
diff --git a/target-avr/translate.c b/target-avr/translate.c
index e98aaef..0df0184 100644
--- a/target-avr/translate.c
+++ b/target-avr/translate.c
@@ -18,60 +18,31 @@
  *  
  */
 
-#include "qemu/osdep.h"
-
-#include "cpu.h"
-#include "exec/exec-all.h"
-#include "disas/disas.h"
-#include "tcg-op.h"
-#include "exec/cpu_ldst.h"
-
-#include "exec/helper-proto.h"
-#include "exec/helper-gen.h"
-#include "exec/log.h"
-
-typedef struct DisasContext DisasContext;
-typedef struct InstInfo InstInfo;
-
-/*This is the state at translation time.  */
-struct DisasContext {
-struct TranslationBlock*tb;
-
-/*Routine used to access memory */
-int memidx;
-int bstate;
-int singlestep;
-};
-
-enum {
-BS_NONE = 0,/*  Nothing special (none of the below  */
-BS_STOP = 1,/*  We want to stop translation for any reason  */
-BS_BRANCH   = 2,/*  A branch condition is reached   */
-BS_EXCP = 3,/*  An exception condition is reached   */
-};
-
-static TCGv_env cpu_env;
-
-static TCGv cpu_pc;
-
-static TCGv cpu_Cf;
-static TCGv cpu_Zf;
-static TCGv cpu_Nf;
-static TCGv cpu_Vf;
-static TCGv cpu_Sf;
-static TCGv cpu_Hf;
-static TCGv cpu_Tf;
-static TCGv cpu_If;
-
-static TCGv cpu_rampD;
-static TCGv cpu_rampX;
-static TCGv cpu_rampY;
-static TCGv cpu_rampZ;
-
-static TCGv cpu_io[64];
-static TCGv cpu_r[32];
-static TCGv cpu_eind;
-static TCGv cpu_sp;
+#include "translate.h"
+
+
+TCGv_env cpu_env;
+
+TCGv cpu_pc;
+
+TCGv cpu_Cf;
+TCGv cpu_Zf;
+TCGv cpu_Nf;
+TCGv cpu_Vf;
+TCGv cpu_Sf;
+TCGv cpu_Hf;
+TCGv cpu_Tf;
+TCGv cpu_If;
+
+TCGv cpu_rampD;
+TCGv cpu_rampX;
+TCGv cpu_rampY;
+TCGv cpu_rampZ;
+
+TCGv cpu_io[64];
+TCGv cpu_r[32];
+TCGv cpu_eind;
+TCGv cpu_sp;
 
 #include "exec/gen-icount.h"
 #define REG(x)  (cpu_r[x])
@@ -120,30 +91,42 @@ voidavr_translate_init(void)
 done_init = 1;
 }
 
-static inline void  gen_goto_tb(CPUAVRState*env,
-DisasContext   *ctx,
-int n,
-target_ulongdest)
+static void decode_opc(
+AVRCPU *cpu,
+DisasContext   *ctx,
+InstInfo   *inst)
 {
-TranslationBlock   *tb;
+CPUAVRState*env = >env;
 
-tb  = ctx->tb;
+inst->opcode= cpu_ldl_code(env, inst->cpc * 2);   /*  pc points to 
words*/
+inst->length= 16;
+inst->translate = NULL;
 
-if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)
-&&  (ctx->singlestep == 0)) {
-tcg_gen_goto_tb(n);
-tcg_gen_movi_i32(cpu_pc, dest);
-tcg_gen_exit_tb((uintptr_t)tb + n);
-} else {
-tcg_gen_movi_i32(cpu_pc, dest);
+/*  the following function looks onto the opcode as a string of bytes   */
+avr_decode(inst->cpc, >length, inst->opcode, >translate);
 
-if (ctx->singlestep) {
-gen_helper_debug(cpu_env);
-}
-tcg_gen_exit_tb(0);
+if (inst->length == 16) {
+inst->npc= inst->cpc + 1;
+/*  get opcode as 16bit value   */
+inst->opcode = inst->opcode & 0x;
+}
+if (inst->length == 32) {
+inst->npc= inst->cpc + 2;
+/*  get opcode as 32bit value   */
+inst->opcode = (inst->opcode << 16)
+ | (inst->opcode >> 16);
 }
 }
 
+uint32_tget_opcode(
+uint8_t const  *code,
+unsignedbitBase,
+unsignedbitSize)
+{
+return  *(uint16_t *)code;
+}
+
+
 /*generate intermediate code for basic block 'tb'.  */
 voidgen_intermediate_code(
 CPUAVRState*env,
@@ -176,18 +159,21 @@ voidgen_intermediate_code(
 gen_tb_start(tb);
 
 /*  decode first instruction*/
-cpc = pc_start;
-npc = cpc + 1;
+ctx.inst[0].cpc = pc_start;
+decode_opc(cpu, ,