Re: [Qemu-devel] [PATCH 2/2] ppc: Allow 64kiB pages for POWER8 in TCG

2016-01-11 Thread David Gibson 
On Fri, Jan 08, 2016 at 02:56:02PM +1100, Alexey Kardashevskiy wrote:
> On 12/21/2015 01:41 PM, David Gibson wrote:
> >Now that the spapr code has been extended to support 64kiB pages, we can
> >allow guests to use 64kiB pages on an emulated POWER8 by adding it to the
> >"segment_page_sizes" structure which is advertised via the device tree.
> >
> >For now we just add support for 64kiB pages in 64kiB page segments.  Real
> >POWER8 also supports 64kiB pages in 4kiB page segments, but that will
> >require more work to implement.
> >
> >Real POWER7s (and maybe some other CPU models) also support 64kiB pages,
> >however, I don't want to add support there without double checking if they
> >use the same HPTE and SLB encodings (in principle these are implementation
> >dependent).
> >
> >Signed-off-by: David Gibson 
> >---
> >  target-ppc/translate_init.c | 17 +
> >  1 file changed, 17 insertions(+)
> >
> >diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> >index e88dc7f..ae5a269 100644
> >--- a/target-ppc/translate_init.c
> >+++ b/target-ppc/translate_init.c
> >@@ -8200,6 +8200,22 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> >  {
> >  DeviceClass *dc = DEVICE_CLASS(oc);
> >  PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> >+static const struct ppc_segment_page_sizes POWER8_sps = {
> >+.sps = {
> >+{ .page_shift = 12, /* 4K */
> >+  .slb_enc = 0,
> >+  .enc = { { .page_shift = 12, .pte_enc = 0 } }
> >+},
> >+{ .page_shift = 16, /* 64K */
> >+  .slb_enc = 0x110,
> >+  .enc = { { .page_shift = 16, .pte_enc = 0x1 } }
> >+},
> >+{ .page_shift = 24, /* 16M */
> >+  .slb_enc = 0x100,
> >+  .enc = { { .page_shift = 24, .pte_enc = 0 } }
> >+},
> >+}
> >+};
> 
> 
> In order to educate myself - where did 0x110/0x100 come from?

These are the L and LP bit encodings used by actual POWER8 hardware -
IIRC I took the information from the kernel's mmu_psize_defs table.

> Is not 0x110
> SLB_VSID_64K (which does not use SLB_VSID_L by accident?)?

Yes, it is

> And is 0x100
> SLB_VSID_L?

Yes.

> I just wanted to double check if POWER7 uses the same encoding and it is not
> that simple to trace what came from where...
> 
> 
> 
> >
> >  dc->fw_name = "PowerPC,POWER8";
> >  dc->desc = "POWER8";
> >@@ -8258,6 +8274,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> >  pcc->l1_dcache_size = 0x8000;
> >  pcc->l1_icache_size = 0x8000;
> >  pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> >+pcc->sps = _sps;
> >  }
> >  #endif /* defined (TARGET_PPC64) */
> >
> >
> 
> 

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [Qemu-devel] [PATCH 2/2] ppc: Allow 64kiB pages for POWER8 in TCG

2016-01-11 Thread Alexey Kardashevskiy 

On 01/12/2016 03:33 PM, David Gibson wrote:

On Tue, Jan 12, 2016 at 03:30:33PM +1100, Alexey Kardashevskiy wrote:

On 01/12/2016 11:26 AM, David Gibson wrote:

On Fri, Jan 08, 2016 at 02:56:02PM +1100, Alexey Kardashevskiy wrote:

On 12/21/2015 01:41 PM, David Gibson wrote:

Now that the spapr code has been extended to support 64kiB pages, we can
allow guests to use 64kiB pages on an emulated POWER8 by adding it to the
"segment_page_sizes" structure which is advertised via the device tree.

For now we just add support for 64kiB pages in 64kiB page segments.  Real
POWER8 also supports 64kiB pages in 4kiB page segments, but that will
require more work to implement.

Real POWER7s (and maybe some other CPU models) also support 64kiB pages,
however, I don't want to add support there without double checking if they
use the same HPTE and SLB encodings (in principle these are implementation
dependent).

Signed-off-by: David Gibson 
---
  target-ppc/translate_init.c | 17 +
  1 file changed, 17 insertions(+)

diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index e88dc7f..ae5a269 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8200,6 +8200,22 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
  {
  DeviceClass *dc = DEVICE_CLASS(oc);
  PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+static const struct ppc_segment_page_sizes POWER8_sps = {
+.sps = {
+{ .page_shift = 12, /* 4K */
+  .slb_enc = 0,
+  .enc = { { .page_shift = 12, .pte_enc = 0 } }
+},
+{ .page_shift = 16, /* 64K */
+  .slb_enc = 0x110,
+  .enc = { { .page_shift = 16, .pte_enc = 0x1 } }
+},
+{ .page_shift = 24, /* 16M */
+  .slb_enc = 0x100,
+  .enc = { { .page_shift = 24, .pte_enc = 0 } }
+},
+}
+};



In order to educate myself - where did 0x110/0x100 come from?


These are the L and LP bit encodings used by actual POWER8 hardware -
IIRC I took the information from the kernel's mmu_psize_defs table.



I found this in p8-book4. Paul suggested there is a public POWER8 user
manual but I cannot neither google it nor find on
http://openpowerfoundation.org/.


Ok.



Ah. Forgot the main point - this encoding is the same in P7_BookIV so this 
could be used for P7 as well.









Is not 0x110
SLB_VSID_64K (which does not use SLB_VSID_L by accident?)?


Yes, it is


And is 0x100
SLB_VSID_L?


Yes.


Cool, thanks.

btw why not to use those definitions then...


I think I started trying to, but got into some #include complications
that weren't worth the hassling of sorting out at the time.


A bit weird but ok.


--
Alexey

Re: [Qemu-devel] [PATCH 2/2] ppc: Allow 64kiB pages for POWER8 in TCG

2016-01-11 Thread Alexey Kardashevskiy 

On 01/12/2016 11:26 AM, David Gibson wrote:

On Fri, Jan 08, 2016 at 02:56:02PM +1100, Alexey Kardashevskiy wrote:

On 12/21/2015 01:41 PM, David Gibson wrote:

Now that the spapr code has been extended to support 64kiB pages, we can
allow guests to use 64kiB pages on an emulated POWER8 by adding it to the
"segment_page_sizes" structure which is advertised via the device tree.

For now we just add support for 64kiB pages in 64kiB page segments.  Real
POWER8 also supports 64kiB pages in 4kiB page segments, but that will
require more work to implement.

Real POWER7s (and maybe some other CPU models) also support 64kiB pages,
however, I don't want to add support there without double checking if they
use the same HPTE and SLB encodings (in principle these are implementation
dependent).

Signed-off-by: David Gibson 
---
  target-ppc/translate_init.c | 17 +
  1 file changed, 17 insertions(+)

diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index e88dc7f..ae5a269 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8200,6 +8200,22 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
  {
  DeviceClass *dc = DEVICE_CLASS(oc);
  PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+static const struct ppc_segment_page_sizes POWER8_sps = {
+.sps = {
+{ .page_shift = 12, /* 4K */
+  .slb_enc = 0,
+  .enc = { { .page_shift = 12, .pte_enc = 0 } }
+},
+{ .page_shift = 16, /* 64K */
+  .slb_enc = 0x110,
+  .enc = { { .page_shift = 16, .pte_enc = 0x1 } }
+},
+{ .page_shift = 24, /* 16M */
+  .slb_enc = 0x100,
+  .enc = { { .page_shift = 24, .pte_enc = 0 } }
+},
+}
+};



In order to educate myself - where did 0x110/0x100 come from?


These are the L and LP bit encodings used by actual POWER8 hardware -
IIRC I took the information from the kernel's mmu_psize_defs table.



I found this in p8-book4. Paul suggested there is a public POWER8 user 
manual but I cannot neither google it nor find on 
http://openpowerfoundation.org/.




Is not 0x110
SLB_VSID_64K (which does not use SLB_VSID_L by accident?)?


Yes, it is


And is 0x100
SLB_VSID_L?


Yes.


Cool, thanks.

btw why not to use those definitions then...





I just wanted to double check if POWER7 uses the same encoding and it is not
that simple to trace what came from where...





  dc->fw_name = "PowerPC,POWER8";
  dc->desc = "POWER8";
@@ -8258,6 +8274,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
  pcc->l1_dcache_size = 0x8000;
  pcc->l1_icache_size = 0x8000;
  pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+pcc->sps = _sps;
  }
  #endif /* defined (TARGET_PPC64) */










--
Alexey

Re: [Qemu-devel] [PATCH 2/2] ppc: Allow 64kiB pages for POWER8 in TCG

2016-01-11 Thread David Gibson 
On Tue, Jan 12, 2016 at 03:30:33PM +1100, Alexey Kardashevskiy wrote:
> On 01/12/2016 11:26 AM, David Gibson wrote:
> >On Fri, Jan 08, 2016 at 02:56:02PM +1100, Alexey Kardashevskiy wrote:
> >>On 12/21/2015 01:41 PM, David Gibson wrote:
> >>>Now that the spapr code has been extended to support 64kiB pages, we can
> >>>allow guests to use 64kiB pages on an emulated POWER8 by adding it to the
> >>>"segment_page_sizes" structure which is advertised via the device tree.
> >>>
> >>>For now we just add support for 64kiB pages in 64kiB page segments.  Real
> >>>POWER8 also supports 64kiB pages in 4kiB page segments, but that will
> >>>require more work to implement.
> >>>
> >>>Real POWER7s (and maybe some other CPU models) also support 64kiB pages,
> >>>however, I don't want to add support there without double checking if they
> >>>use the same HPTE and SLB encodings (in principle these are implementation
> >>>dependent).
> >>>
> >>>Signed-off-by: David Gibson 
> >>>---
> >>>  target-ppc/translate_init.c | 17 +
> >>>  1 file changed, 17 insertions(+)
> >>>
> >>>diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> >>>index e88dc7f..ae5a269 100644
> >>>--- a/target-ppc/translate_init.c
> >>>+++ b/target-ppc/translate_init.c
> >>>@@ -8200,6 +8200,22 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
> >>>  {
> >>>  DeviceClass *dc = DEVICE_CLASS(oc);
> >>>  PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> >>>+static const struct ppc_segment_page_sizes POWER8_sps = {
> >>>+.sps = {
> >>>+{ .page_shift = 12, /* 4K */
> >>>+  .slb_enc = 0,
> >>>+  .enc = { { .page_shift = 12, .pte_enc = 0 } }
> >>>+},
> >>>+{ .page_shift = 16, /* 64K */
> >>>+  .slb_enc = 0x110,
> >>>+  .enc = { { .page_shift = 16, .pte_enc = 0x1 } }
> >>>+},
> >>>+{ .page_shift = 24, /* 16M */
> >>>+  .slb_enc = 0x100,
> >>>+  .enc = { { .page_shift = 24, .pte_enc = 0 } }
> >>>+},
> >>>+}
> >>>+};
> >>
> >>
> >>In order to educate myself - where did 0x110/0x100 come from?
> >
> >These are the L and LP bit encodings used by actual POWER8 hardware -
> >IIRC I took the information from the kernel's mmu_psize_defs table.
> 
> 
> I found this in p8-book4. Paul suggested there is a public POWER8 user
> manual but I cannot neither google it nor find on
> http://openpowerfoundation.org/.

Ok.

> 
> 
> >>Is not 0x110
> >>SLB_VSID_64K (which does not use SLB_VSID_L by accident?)?
> >
> >Yes, it is
> >
> >>And is 0x100
> >>SLB_VSID_L?
> >
> >Yes.
> 
> Cool, thanks.
> 
> btw why not to use those definitions then...

I think I started trying to, but got into some #include complications
that weren't worth the hassling of sorting out at the time.

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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Re: [Qemu-devel] [PATCH 2/2] ppc: Allow 64kiB pages for POWER8 in TCG

2016-01-07 Thread Alexey Kardashevskiy 

On 12/21/2015 01:41 PM, David Gibson wrote:

Now that the spapr code has been extended to support 64kiB pages, we can
allow guests to use 64kiB pages on an emulated POWER8 by adding it to the
"segment_page_sizes" structure which is advertised via the device tree.

For now we just add support for 64kiB pages in 64kiB page segments.  Real
POWER8 also supports 64kiB pages in 4kiB page segments, but that will
require more work to implement.

Real POWER7s (and maybe some other CPU models) also support 64kiB pages,
however, I don't want to add support there without double checking if they
use the same HPTE and SLB encodings (in principle these are implementation
dependent).

Signed-off-by: David Gibson 
---
  target-ppc/translate_init.c | 17 +
  1 file changed, 17 insertions(+)

diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index e88dc7f..ae5a269 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8200,6 +8200,22 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
  {
  DeviceClass *dc = DEVICE_CLASS(oc);
  PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+static const struct ppc_segment_page_sizes POWER8_sps = {
+.sps = {
+{ .page_shift = 12, /* 4K */
+  .slb_enc = 0,
+  .enc = { { .page_shift = 12, .pte_enc = 0 } }
+},
+{ .page_shift = 16, /* 64K */
+  .slb_enc = 0x110,
+  .enc = { { .page_shift = 16, .pte_enc = 0x1 } }
+},
+{ .page_shift = 24, /* 16M */
+  .slb_enc = 0x100,
+  .enc = { { .page_shift = 24, .pte_enc = 0 } }
+},
+}
+};



In order to educate myself - where did 0x110/0x100 come from? Is not 0x110 
SLB_VSID_64K (which does not use SLB_VSID_L by accident?)? And is 0x100 
SLB_VSID_L?


I just wanted to double check if POWER7 uses the same encoding and it is 
not that simple to trace what came from where...






  dc->fw_name = "PowerPC,POWER8";
  dc->desc = "POWER8";
@@ -8258,6 +8274,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
  pcc->l1_dcache_size = 0x8000;
  pcc->l1_icache_size = 0x8000;
  pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+pcc->sps = _sps;
  }
  #endif /* defined (TARGET_PPC64) */





--
Alexey

[Qemu-devel] [PATCH 2/2] ppc: Allow 64kiB pages for POWER8 in TCG

2015-12-20 Thread David Gibson 
Now that the spapr code has been extended to support 64kiB pages, we can
allow guests to use 64kiB pages on an emulated POWER8 by adding it to the
"segment_page_sizes" structure which is advertised via the device tree.

For now we just add support for 64kiB pages in 64kiB page segments.  Real
POWER8 also supports 64kiB pages in 4kiB page segments, but that will
require more work to implement.

Real POWER7s (and maybe some other CPU models) also support 64kiB pages,
however, I don't want to add support there without double checking if they
use the same HPTE and SLB encodings (in principle these are implementation
dependent).

Signed-off-by: David Gibson 
---
 target-ppc/translate_init.c | 17 +
 1 file changed, 17 insertions(+)

diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index e88dc7f..ae5a269 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8200,6 +8200,22 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
 {
 DeviceClass *dc = DEVICE_CLASS(oc);
 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+static const struct ppc_segment_page_sizes POWER8_sps = {
+.sps = {
+{ .page_shift = 12, /* 4K */
+  .slb_enc = 0,
+  .enc = { { .page_shift = 12, .pte_enc = 0 } }
+},
+{ .page_shift = 16, /* 64K */
+  .slb_enc = 0x110,
+  .enc = { { .page_shift = 16, .pte_enc = 0x1 } }
+},
+{ .page_shift = 24, /* 16M */
+  .slb_enc = 0x100,
+  .enc = { { .page_shift = 24, .pte_enc = 0 } }
+},
+}
+};
 
 dc->fw_name = "PowerPC,POWER8";
 dc->desc = "POWER8";
@@ -8258,6 +8274,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
 pcc->l1_dcache_size = 0x8000;
 pcc->l1_icache_size = 0x8000;
 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+pcc->sps = _sps;
 }
 #endif /* defined (TARGET_PPC64) */
 
-- 
2.5.0

Re: [Qemu-devel] [PATCH 2/2] ppc: Allow 64kiB pages for POWER8 in TCG

2015-12-20 Thread Benjamin Herrenschmidt 
On Mon, 2015-12-21 at 13:41 +1100, David Gibson wrote:
> Now that the spapr code has been extended to support 64kiB pages, we can
> allow guests to use 64kiB pages on an emulated POWER8 by adding it to the
> "segment_page_sizes" structure which is advertised via the device tree.
> 
> For now we just add support for 64kiB pages in 64kiB page segments.  Real
> POWER8 also supports 64kiB pages in 4kiB page segments, but that will
> require more work to implement.
> 
> Real POWER7s (and maybe some other CPU models) also support 64kiB pages,
> however, I don't want to add support there without double checking if they
> use the same HPTE and SLB encodings (in principle these are implementation
> dependent).

Don't I have a patch for that in my series already ? IIRC, I had
another fix somewhere...

https://github.com/ozbenh/qemu/commit/6c9dc80db82ed87d5ee77852930348232
f5f9db2

Cheers,
Ben.


> Signed-off-by: David Gibson 
> ---
>  target-ppc/translate_init.c | 17 +
>  1 file changed, 17 insertions(+)
> 
> diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
> index e88dc7f..ae5a269 100644
> --- a/target-ppc/translate_init.c
> +++ b/target-ppc/translate_init.c
> @@ -8200,6 +8200,22 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>  {
>  DeviceClass *dc = DEVICE_CLASS(oc);
>  PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> +static const struct ppc_segment_page_sizes POWER8_sps = {
> +.sps = {
> +{ .page_shift = 12, /* 4K */
> +  .slb_enc = 0,
> +  .enc = { { .page_shift = 12, .pte_enc = 0 } }
> +},
> +{ .page_shift = 16, /* 64K */
> +  .slb_enc = 0x110,
> +  .enc = { { .page_shift = 16, .pte_enc = 0x1 } }
> +},
> +{ .page_shift = 24, /* 16M */
> +  .slb_enc = 0x100,
> +  .enc = { { .page_shift = 24, .pte_enc = 0 } }
> +},
> +}
> +};
>  
>  dc->fw_name = "PowerPC,POWER8";
>  dc->desc = "POWER8";
> @@ -8258,6 +8274,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>  pcc->l1_dcache_size = 0x8000;
>  pcc->l1_icache_size = 0x8000;
>  pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
> +pcc->sps = _sps;
>  }
>  #endif /* defined (TARGET_PPC64) */
>