Re: [Qemu-devel] [PATCH RFC 4/9] tcg/optimize: add optimizations for ext_i32_i64 and extu_i32_i64 ops

2015-07-17 Thread Richard Henderson 

On 07/15/2015 12:03 PM, Aurelien Jarno wrote:

They behave the same as ext32s_i64 and ext32u_i64 from the constant
folding and zero propagation point of view, except that they can't
be replaced by a mov, so we don't compute the affected value.

Cc: Paolo Bonzinipbonz...@redhat.com
Cc: Richard Hendersonr...@twiddle.net
Signed-off-by: Aurelien Jarnoaurel...@aurel32.net
---
  tcg/optimize.c | 10 ++
  1 file changed, 10 insertions(+)


Reviewed-by: Richard Henderson r...@twiddle.net


r~

[Qemu-devel] [PATCH RFC 4/9] tcg/optimize: add optimizations for ext_i32_i64 and extu_i32_i64 ops

2015-07-15 Thread Aurelien Jarno 
They behave the same as ext32s_i64 and ext32u_i64 from the constant
folding and zero propagation point of view, except that they can't
be replaced by a mov, so we don't compute the affected value.

Cc: Paolo Bonzini pbonz...@redhat.com
Cc: Richard Henderson r...@twiddle.net
Signed-off-by: Aurelien Jarno aurel...@aurel32.net
---
 tcg/optimize.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/tcg/optimize.c b/tcg/optimize.c
index d66373d..18b7bc3 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -347,9 +347,11 @@ static TCGArg do_constant_folding_2(TCGOpcode op, TCGArg 
x, TCGArg y)
 CASE_OP_32_64(ext16u):
 return (uint16_t)x;
 
+case INDEX_op_ext_i32_i64:
 case INDEX_op_ext32s_i64:
 return (int32_t)x;
 
+case INDEX_op_extu_i32_i64:
 case INDEX_op_ext32u_i64:
 return (uint32_t)x;
 
@@ -839,6 +841,14 @@ void tcg_optimize(TCGContext *s)
 mask = temps[args[1]].mask  mask;
 break;
 
+case INDEX_op_ext_i32_i64:
+if ((temps[args[1]].mask  0x8000) != 0) {
+break;
+}
+case INDEX_op_extu_i32_i64:
+mask = (uint32_t)temps[args[1]].mask;
+break;
+
 CASE_OP_32_64(andc):
 /* Known-zeros does not imply known-ones.  Therefore unless
args[2] is constant, we can't infer anything from it.  */
-- 
2.1.4