Re: [Qemu-devel] [PATCH RFC v3 00/11] Add RX archtecture support
On Thu, 21 Mar 2019 10:35:07 +0900,
Richard Henderson wrote:
>
> On 3/20/19 7:05 AM, Yoshinori Sato wrote:
> > OK. fixed another way.
> > But RX big-endian mode only data access.
> > So operand value always little-endian order.
>
> Oh that is convenient.
> Therefore the operand can always be put together by pieces. E.g.
>
> -%b4_dsp_16 0:16 !function=dsp16
> -%b4_bdsp 0:24 !function=bdsp_a
> +%b4_dsp16 0:s8 8:8
> +%b4_dsp24 0:s8 8:8 16:8
>
> Also note the 's' qualifier that defines signed fields.
>
> -%b2_bdsp 16:8 !function=bdsp_b
> ...
> -@b2_bcnd_b cd:4 dsp=%b2_bdsp sz=2
> -@b2_bra_b dsp=%b2_bdsp sz=2
> +@b2_bcnd_b cd:4 dsp:s8 sz=2
> +@b2_bra_b dsp:s8 sz=2
>
OK.
>
> >>> +/* push rs */
> >>> +static bool trans_PUSH_r(DisasContext *ctx, arg_PUSH_r *a)
> >>> +{
> >>> +if (a->rs != 0) {
> >>> +tcg_gen_subi_i32(cpu_regs[0], cpu_regs[0], 4);
> >>> +rx_gen_ldst(a->sz, RX_MEMORY_ST, cpu_regs[a->rs], cpu_regs[0]);
> >>> +} else {
> >>> +tcg_gen_mov_i32(ctx->src, cpu_regs[a->rs]);
> >>> +tcg_gen_subi_i32(cpu_regs[0], cpu_regs[0], 4);
> >>> +rx_gen_ldst(a->sz, RX_MEMORY_ST, ctx->src, cpu_regs[0]);
> >>> +}
> >>> +return true;
> >>
> >> As far as I can see the THEN and ELSE cases have identical operation.
> >
> > It little different.
> > In the case of r0, the value before decrementing is stored in memory.
> > I added comment.
>
> What I mean is that the sequence that you use for r0 could also be used for
> all
> other rN.
>
> I understand that RX does not have an mmu, but the normal way we handle this
> is
>
> tcg_gen_subi_i32(addr, cpu_regs[0], 4);
> rx_gen_st(a->sz, cpu_regs[a->rs], addr);
> tcg_gen_mov_i32(cpu_regs[0], addr);
>
> so that the stack pointer is not modified if the store raises an exception.
>
r0 is stack pointer.
The push / pop instructions read and write the address indicated by r0.
This part is complicated, so let's fix it a little more.
It should be able to expand into transfer instruction of
pre-decrement and post-increment.
>
> r~
>
--
Yosinori Sato
Re: [Qemu-devel] [PATCH RFC v3 00/11] Add RX archtecture support
On 3/20/19 7:05 AM, Yoshinori Sato wrote:
> OK. fixed another way.
> But RX big-endian mode only data access.
> So operand value always little-endian order.
Oh that is convenient.
Therefore the operand can always be put together by pieces. E.g.
-%b4_dsp_16 0:16 !function=dsp16
-%b4_bdsp 0:24 !function=bdsp_a
+%b4_dsp16 0:s8 8:8
+%b4_dsp24 0:s8 8:8 16:8
Also note the 's' qualifier that defines signed fields.
-%b2_bdsp 16:8 !function=bdsp_b
...
-@b2_bcnd_b cd:4 dsp=%b2_bdsp sz=2
-@b2_bra_b dsp=%b2_bdsp sz=2
+@b2_bcnd_b cd:4 dsp:s8 sz=2
+@b2_bra_b dsp:s8 sz=2
>>> +/* push rs */
>>> +static bool trans_PUSH_r(DisasContext *ctx, arg_PUSH_r *a)
>>> +{
>>> +if (a->rs != 0) {
>>> +tcg_gen_subi_i32(cpu_regs[0], cpu_regs[0], 4);
>>> +rx_gen_ldst(a->sz, RX_MEMORY_ST, cpu_regs[a->rs], cpu_regs[0]);
>>> +} else {
>>> +tcg_gen_mov_i32(ctx->src, cpu_regs[a->rs]);
>>> +tcg_gen_subi_i32(cpu_regs[0], cpu_regs[0], 4);
>>> +rx_gen_ldst(a->sz, RX_MEMORY_ST, ctx->src, cpu_regs[0]);
>>> +}
>>> +return true;
>>
>> As far as I can see the THEN and ELSE cases have identical operation.
>
> It little different.
> In the case of r0, the value before decrementing is stored in memory.
> I added comment.
What I mean is that the sequence that you use for r0 could also be used for all
other rN.
I understand that RX does not have an mmu, but the normal way we handle this is
tcg_gen_subi_i32(addr, cpu_regs[0], 4);
rx_gen_st(a->sz, cpu_regs[a->rs], addr);
tcg_gen_mov_i32(cpu_regs[0], addr);
so that the stack pointer is not modified if the store raises an exception.
r~
Re: [Qemu-devel] [PATCH RFC v3 00/11] Add RX archtecture support
On Fri, 08 Mar 2019 10:24:23 +0900,
Richard Henderson wrote:
>
> On 3/1/19 10:21 PM, Yoshinori Sato wrote:
> > My git repository is bellow.
> > git://git.pf.osdn.net/gitroot/y/ys/ysato/qemu.git
>
> Somehow patch 1 did not arrive, so I am reviewing based on
> rebasing this branch against master, and then looking at the diff.
>
> > +struct CCop;
>
> Unused?
Yes. I forgot remove.
Remove it.
> > +static inline void cpu_get_tb_cpu_state(CPURXState *env, target_ulong *pc,
> > +target_ulong *cs_base, uint32_t
> > *flags)
> > +{
> > +*pc = env->pc;
> > +*cs_base = 0;
> > +*flags = 0;
> > +}
>
> *flags should contain PSW[PM], I think, so that knowledge of the
> privilege level is given to the translator.
>
> Looking forward I see that you're currently testing cpu_psw_pm dynamically for
> instructions that require privs, so what you have is not wrong, but this is
> exactly the sort of thing that TB flags are for.
OK.
Update PSW.PM copy to DisasContextBase.flags.
> > +#define RX_PSW_OP_NEG 4
>
> Unused?
Yes. Remove it.
> > +#define RX_BYTE 0
> > +#define RX_WORD 1
> > +#define RX_LONG 2
>
> Redundant with TCGMemOps: MO_8, MO_16, MO_32?
OK. Convert it.
> > +++ b/target/rx/insns.decode
>
> Should have a copyright + license notice.
>
> > +BCnd_b 0010 cd:4 dsp:8
> ...
> > +#BRA_b 0010 1110 dsp:8 # overlaps BCnd_b
>
> FYI, using pattern groups this can be written
>
> {
> BRA_b0010 1110 dsp:8
> Bcnd_b 0010 cd:4 dsp:8
> }
>
> I expect to have pattern groups merged this week.
OK. Update pattern groups.
> > +static void rx_tr_init_disas_context(DisasContextBase *dcbase, CPUState
> > *cs)
> > +{
> > +DisasContext *ctx = container_of(dcbase, DisasContext, base);
> > +
> > +ctx->src = tcg_temp_new();
> > +}
>
> This allocation will not survive across a branch or label.
> So, after any SHIFTR_REG, for instance.
>
> I think you need to allocate this on demand each insn, and
> free it as necessary after each insn.
>
> (Although avoiding branches in tcg is always helpful.)
OK. Remove it.
> > +/* generic load / store wrapper */
> > +static inline void rx_gen_ldst(unsigned int size, unsigned int dir,
> > +TCGv reg, TCGv mem)
> > +{
> > +if (dir) {
> > +tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_SIGN | MO_TE);
> > +} else {
> > +tcg_gen_qemu_st_i32(reg, mem, 0, size | MO_TE);
> > +}
> > +}
>
> It would probably be worthwhile to split this function, and drop the "dir"
> parameter. It is always a constant, so instead of
>
> rx_gen_ldst(mi, RX_MEMORY_LD, ctx->src, ctx->src);
> rx_gen_ldst(a->sz, RX_MEMORY_ST, cpu_regs[a->rs], ctx->src);
>
> use the shorter
>
> rx_gen_ld(mi, ctx->src, ctx->src);
> rx_gen_st(a->sz, cpu_regs[a->rs], ctx->src);
OK. fixed
>
> > +/* mov.l #uimm4,rd */
> > +/* mov.l #uimm8,rd */
> > +static bool trans_MOV_ri(DisasContext *ctx, arg_MOV_ri *a)
> > +{
> > +tcg_gen_movi_i32(cpu_regs[a->rd], a->imm & 0xff);
> > +return true;
> > +}
>
> a->imm will already have been masked by the decode.
> You can drop the & 0xff here.
That was right.
It seems that I was misunderstood.
> > +/* mov.l #imm,rd */
> > +static bool trans_MOV_rli(DisasContext *ctx, arg_MOV_rli *a)
> > +{
> > +tcg_gen_movi_i32(cpu_regs[a->rd], a->imm);
> > +return true;
> > +}
>
> As written, this function is redundant. We should be using the same MOV_ri,
> with the immediate loaded from %b2_li_2.
>
> Likewise for trans_MOV_mi vs trans_MOV_mli. That said...
OK. Unified various interger instructions.
> > +static bool trans_MOV_mli(DisasContext *ctx, arg_MOV_mli *a)
> > +{
> > +TCGv imm = tcg_const_i32(a->imm);
> > +if (a->ld == 2) {
> > +a->dsp = bswap_16(a->dsp);
> > +}
>
> This suggests that the decode is incorrect. Or perhaps the construction of
> the
> 32-bit insn passed into decode. In decode_load_bytes, we construct a
> big-endian value, so it would seem this dsp field should be loaded as a
> little-endian value.
>
> This could be fixed by not attempting to load the LI constant in decodetree
> (for this insn), which would in turn not require that you decode the LD
> operand
> by hand in decodetree. E.g.
>
> static bool trans_MOV_mli(DisasContext *ctx, arg_MOV_mli *a)
> {
> TCGv imm;
>
> /* dsp operand comes before immediate operand */
> rx_index_addr(a->ld, a->sz, a->rd, s);
> imm = tcg_const_i32(li(s, a->li));
> rx_gen_st(a->sz, imm, ctx->src);
> tcg_temp_free_i32(imm);
> return true;
> }
>
> This will be easiest if you ever support the big-endian version of RX.
OK. fixed another way.
But RX big-endian mode only data access.
So operand value always little-endian order.
> > +/* push rs */
> > +static bool trans_PUSH_r(DisasContext *ctx, arg_PUSH_r *a)
> > +{
> > +if (a->rs != 0) {
> > +tcg_gen_subi_i32(cpu_regs[0], cpu_regs[0], 4);
> >
Re: [Qemu-devel] [PATCH RFC v3 00/11] Add RX archtecture support
On 3/1/19 10:21 PM, Yoshinori Sato wrote:
> My git repository is bellow.
> git://git.pf.osdn.net/gitroot/y/ys/ysato/qemu.git
Somehow patch 1 did not arrive, so I am reviewing based on
rebasing this branch against master, and then looking at the diff.
> +struct CCop;
Unused?
> +static inline void cpu_get_tb_cpu_state(CPURXState *env, target_ulong *pc,
> +target_ulong *cs_base, uint32_t
> *flags)
> +{
> +*pc = env->pc;
> +*cs_base = 0;
> +*flags = 0;
> +}
*flags should contain PSW[PM], I think, so that knowledge of the
privilege level is given to the translator.
Looking forward I see that you're currently testing cpu_psw_pm dynamically for
instructions that require privs, so what you have is not wrong, but this is
exactly the sort of thing that TB flags are for.
> +#define RX_PSW_OP_NEG 4
Unused?
> +#define RX_BYTE 0
> +#define RX_WORD 1
> +#define RX_LONG 2
Redundant with TCGMemOps: MO_8, MO_16, MO_32?
> +++ b/target/rx/insns.decode
Should have a copyright + license notice.
> +BCnd_b 0010 cd:4 dsp:8
...
> +#BRA_b 0010 1110 dsp:8 # overlaps BCnd_b
FYI, using pattern groups this can be written
{
BRA_b0010 1110 dsp:8
Bcnd_b 0010 cd:4 dsp:8
}
I expect to have pattern groups merged this week.
> +static void rx_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
> +{
> +DisasContext *ctx = container_of(dcbase, DisasContext, base);
> +
> +ctx->src = tcg_temp_new();
> +}
This allocation will not survive across a branch or label.
So, after any SHIFTR_REG, for instance.
I think you need to allocate this on demand each insn, and
free it as necessary after each insn.
(Although avoiding branches in tcg is always helpful.)
> +/* generic load / store wrapper */
> +static inline void rx_gen_ldst(unsigned int size, unsigned int dir,
> +TCGv reg, TCGv mem)
> +{
> +if (dir) {
> +tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_SIGN | MO_TE);
> +} else {
> +tcg_gen_qemu_st_i32(reg, mem, 0, size | MO_TE);
> +}
> +}
It would probably be worthwhile to split this function, and drop the "dir"
parameter. It is always a constant, so instead of
rx_gen_ldst(mi, RX_MEMORY_LD, ctx->src, ctx->src);
rx_gen_ldst(a->sz, RX_MEMORY_ST, cpu_regs[a->rs], ctx->src);
use the shorter
rx_gen_ld(mi, ctx->src, ctx->src);
rx_gen_st(a->sz, cpu_regs[a->rs], ctx->src);
> +/* mov.l #uimm4,rd */
> +/* mov.l #uimm8,rd */
> +static bool trans_MOV_ri(DisasContext *ctx, arg_MOV_ri *a)
> +{
> +tcg_gen_movi_i32(cpu_regs[a->rd], a->imm & 0xff);
> +return true;
> +}
a->imm will already have been masked by the decode.
You can drop the & 0xff here.
> +/* mov.l #imm,rd */
> +static bool trans_MOV_rli(DisasContext *ctx, arg_MOV_rli *a)
> +{
> +tcg_gen_movi_i32(cpu_regs[a->rd], a->imm);
> +return true;
> +}
As written, this function is redundant. We should be using the same MOV_ri,
with the immediate loaded from %b2_li_2.
Likewise for trans_MOV_mi vs trans_MOV_mli. That said...
> +static bool trans_MOV_mli(DisasContext *ctx, arg_MOV_mli *a)
> +{
> +TCGv imm = tcg_const_i32(a->imm);
> +if (a->ld == 2) {
> +a->dsp = bswap_16(a->dsp);
> +}
This suggests that the decode is incorrect. Or perhaps the construction of the
32-bit insn passed into decode. In decode_load_bytes, we construct a
big-endian value, so it would seem this dsp field should be loaded as a
little-endian value.
This could be fixed by not attempting to load the LI constant in decodetree
(for this insn), which would in turn not require that you decode the LD operand
by hand in decodetree. E.g.
static bool trans_MOV_mli(DisasContext *ctx, arg_MOV_mli *a)
{
TCGv imm;
/* dsp operand comes before immediate operand */
rx_index_addr(a->ld, a->sz, a->rd, s);
imm = tcg_const_i32(li(s, a->li));
rx_gen_st(a->sz, imm, ctx->src);
tcg_temp_free_i32(imm);
return true;
}
This will be easiest if you ever support the big-endian version of RX.
> +/* push rs */
> +static bool trans_PUSH_r(DisasContext *ctx, arg_PUSH_r *a)
> +{
> +if (a->rs != 0) {
> +tcg_gen_subi_i32(cpu_regs[0], cpu_regs[0], 4);
> +rx_gen_ldst(a->sz, RX_MEMORY_ST, cpu_regs[a->rs], cpu_regs[0]);
> +} else {
> +tcg_gen_mov_i32(ctx->src, cpu_regs[a->rs]);
> +tcg_gen_subi_i32(cpu_regs[0], cpu_regs[0], 4);
> +rx_gen_ldst(a->sz, RX_MEMORY_ST, ctx->src, cpu_regs[0]);
> +}
> +return true;
As far as I can see the THEN and ELSE cases have identical operation.
> +static bool trans_XCHG_rl(DisasContext *ctx, arg_XCHG_rl *a)
> +{
> +int sz;
> +TCGv tmp;
> +tmp = tcg_temp_new();
> +if (a->ld == 3) {
> + /* xchg rs,rd */
> +tcg_gen_mov_i32(tmp, cpu_regs[a->rs]);
> +tcg_gen_mov_i32(cpu_regs[a->rs], cpu_regs[a->rd]);
> +tcg_gen_mov_i32(cpu_regs[a->rd], tmp);
> +} else {
> +
Re: [Qemu-devel] [PATCH RFC v3 00/11] Add RX archtecture support
On Sun, 03 Mar 2019 03:51:14 +0900, Philippe Mathieu-Daudé wrote: > > Hi Yoshinori, > > On 3/2/19 7:21 AM, Yoshinori Sato wrote: > > Hello. > > This patch series is added Renesas RX target emulation. > > > > My git repository is bellow. > > git://git.pf.osdn.net/gitroot/y/ys/ysato/qemu.git > > > > Since my understanding is not enough, > > I want many comments to make this a good one. > > OK :) > > Can you provide notes about how to test your port? > Such: links to toolchains, how to build, what firmware/OS we can run... OK. toolchain - rx-unknown-linux binutils-2.32 include rx-unknown-linux support. $ configure --target=rx-unknown-linux $ make gcc - please use my git repo. git://git.pf.osdn.net/gitroot/y/ys/ysato/gcc.git rx-trunk $ configure --target=rx-unknown-linux --enable-languages=c --disable-shared \ --disable-threads --with-uclibc --disable-libssp --disable-libquadmath \ --disable-libgomp --disable-libatomic $ make This toolchain can build u-boot / linux. target program. u-boot git://git.pf.osdn.net/gitroot/y/ys/ysato/uboot.git rx pre build binary in bellow. https://osdn.net/users/ysato/pf/qemu/dl/u-boot.bin linux git://git.osdn.net/gitroot/uclinux-h8/linux.git rx https://osdn.net/users/ysato/pf/qemu/dl/zImage Since linux is still incomplete, it may be problematic. > > > > Thanks. > > > > Changes v2 > > Rewrite translate. using decodetree.py > > > > Yoshinori Sato (11): > > target/rx: TCG Translation > > target/rx: TCG helper > > target/rx: CPU definition > > target/rx: RX disassembler > > target/rx: miscellaneous functions > > RX62N interrupt contorol uint > > RX62N internal timer modules > > RX62N internal serial communication interface > > RX Target hardware definition > > Add rx-softmmu > > MAINTAINERS: Add RX entry. > > > > MAINTAINERS| 20 + > > arch_init.c|2 + > > configure |8 + > > default-configs/rx-softmmu.mak |7 + > > hw/char/Makefile.objs |2 +- > > hw/char/renesas_sci.c | 288 ++ > > hw/intc/Makefile.objs |1 + > > hw/intc/rx_icu.c | 323 ++ > > hw/rx/Makefile.objs|1 + > > hw/rx/rx62n.c | 227 > > hw/rx/rxqemu.c | 100 ++ > > hw/timer/Makefile.objs |2 + > > hw/timer/renesas_cmt.c | 235 + > > hw/timer/renesas_tmr.c | 412 > > include/disas/bfd.h|5 + > > include/hw/char/renesas_sci.h | 42 + > > include/hw/intc/rx_icu.h | 49 + > > include/hw/rx/rx.h |7 + > > include/hw/rx/rx62n.h | 54 + > > include/hw/timer/renesas_cmt.h | 33 + > > include/hw/timer/renesas_tmr.h | 42 + > > include/sysemu/arch_init.h |1 + > > target/rx/Makefile.objs| 11 + > > target/rx/cpu-qom.h| 52 + > > target/rx/cpu.c| 224 > > target/rx/cpu.h| 214 > > target/rx/disas.c | 1570 > > target/rx/gdbstub.c| 113 ++ > > target/rx/helper.c | 252 + > > target/rx/helper.h | 39 + > > target/rx/insns.decode | 336 ++ > > target/rx/monitor.c| 38 + > > target/rx/op_helper.c | 602 +++ > > target/rx/translate.c | 2220 > > > > 34 files changed, 7531 insertions(+), 1 deletion(-) > > create mode 100644 default-configs/rx-softmmu.mak > > create mode 100644 hw/char/renesas_sci.c > > create mode 100644 hw/intc/rx_icu.c > > create mode 100644 hw/rx/Makefile.objs > > create mode 100644 hw/rx/rx62n.c > > create mode 100644 hw/rx/rxqemu.c > > create mode 100644 hw/timer/renesas_cmt.c > > create mode 100644 hw/timer/renesas_tmr.c > > create mode 100644 include/hw/char/renesas_sci.h > > create mode 100644 include/hw/intc/rx_icu.h > > create mode 100644 include/hw/rx/rx.h > > create mode 100644 include/hw/rx/rx62n.h > > create mode 100644 include/hw/timer/renesas_cmt.h > > create mode 100644 include/hw/timer/renesas_tmr.h > > create mode 100644 target/rx/Makefile.objs > > create mode 100644 target/rx/cpu-qom.h > > create mode 100644 target/rx/cpu.c > > create mode 100644 target/rx/cpu.h > > create mode 100644 target/rx/disas.c > > create mode 100644 target/rx/gdbstub.c > > create mode 100644 target/rx/helper.c > > create mode 100644 target/rx/helper.h > > create mode 100644 target/rx/insns.decode > > create mode 100644 target/rx/monitor.c > > create mode 100644 target/rx/op_helper.c > > create mode 100644 target/rx/translate.c > > > -- Yosinori Sato
Re: [Qemu-devel] [PATCH RFC v3 00/11] Add RX archtecture support
Hi Yoshinori, On 3/2/19 7:21 AM, Yoshinori Sato wrote: > Hello. > This patch series is added Renesas RX target emulation. > > My git repository is bellow. > git://git.pf.osdn.net/gitroot/y/ys/ysato/qemu.git > > Since my understanding is not enough, > I want many comments to make this a good one. OK :) Can you provide notes about how to test your port? Such: links to toolchains, how to build, what firmware/OS we can run... > > Thanks. > > Changes v2 > Rewrite translate. using decodetree.py > > Yoshinori Sato (11): > target/rx: TCG Translation > target/rx: TCG helper > target/rx: CPU definition > target/rx: RX disassembler > target/rx: miscellaneous functions > RX62N interrupt contorol uint > RX62N internal timer modules > RX62N internal serial communication interface > RX Target hardware definition > Add rx-softmmu > MAINTAINERS: Add RX entry. > > MAINTAINERS| 20 + > arch_init.c|2 + > configure |8 + > default-configs/rx-softmmu.mak |7 + > hw/char/Makefile.objs |2 +- > hw/char/renesas_sci.c | 288 ++ > hw/intc/Makefile.objs |1 + > hw/intc/rx_icu.c | 323 ++ > hw/rx/Makefile.objs|1 + > hw/rx/rx62n.c | 227 > hw/rx/rxqemu.c | 100 ++ > hw/timer/Makefile.objs |2 + > hw/timer/renesas_cmt.c | 235 + > hw/timer/renesas_tmr.c | 412 > include/disas/bfd.h|5 + > include/hw/char/renesas_sci.h | 42 + > include/hw/intc/rx_icu.h | 49 + > include/hw/rx/rx.h |7 + > include/hw/rx/rx62n.h | 54 + > include/hw/timer/renesas_cmt.h | 33 + > include/hw/timer/renesas_tmr.h | 42 + > include/sysemu/arch_init.h |1 + > target/rx/Makefile.objs| 11 + > target/rx/cpu-qom.h| 52 + > target/rx/cpu.c| 224 > target/rx/cpu.h| 214 > target/rx/disas.c | 1570 > target/rx/gdbstub.c| 113 ++ > target/rx/helper.c | 252 + > target/rx/helper.h | 39 + > target/rx/insns.decode | 336 ++ > target/rx/monitor.c| 38 + > target/rx/op_helper.c | 602 +++ > target/rx/translate.c | 2220 > > 34 files changed, 7531 insertions(+), 1 deletion(-) > create mode 100644 default-configs/rx-softmmu.mak > create mode 100644 hw/char/renesas_sci.c > create mode 100644 hw/intc/rx_icu.c > create mode 100644 hw/rx/Makefile.objs > create mode 100644 hw/rx/rx62n.c > create mode 100644 hw/rx/rxqemu.c > create mode 100644 hw/timer/renesas_cmt.c > create mode 100644 hw/timer/renesas_tmr.c > create mode 100644 include/hw/char/renesas_sci.h > create mode 100644 include/hw/intc/rx_icu.h > create mode 100644 include/hw/rx/rx.h > create mode 100644 include/hw/rx/rx62n.h > create mode 100644 include/hw/timer/renesas_cmt.h > create mode 100644 include/hw/timer/renesas_tmr.h > create mode 100644 target/rx/Makefile.objs > create mode 100644 target/rx/cpu-qom.h > create mode 100644 target/rx/cpu.c > create mode 100644 target/rx/cpu.h > create mode 100644 target/rx/disas.c > create mode 100644 target/rx/gdbstub.c > create mode 100644 target/rx/helper.c > create mode 100644 target/rx/helper.h > create mode 100644 target/rx/insns.decode > create mode 100644 target/rx/monitor.c > create mode 100644 target/rx/op_helper.c > create mode 100644 target/rx/translate.c >
Re: [Qemu-devel] [PATCH RFC v3 00/11] Add RX archtecture support
Patchew URL: https://patchew.org/QEMU/20190302062138.10713-1-ys...@users.sourceforge.jp/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20190302062138.10713-1-ys...@users.sourceforge.jp Subject: [Qemu-devel] [PATCH RFC v3 00/11] Add RX archtecture support === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 From https://github.com/patchew-project/qemu * [new tag] patchew/20190302062138.10713-1-ys...@users.sourceforge.jp -> patchew/20190302062138.10713-1-ys...@users.sourceforge.jp Switched to a new branch 'test' e60fbb35e6 MAINTAINERS: Add RX entry. 3bdc16f591 Add rx-softmmu 38c0424e72 RX Target hardware definition a6ec852164 RX62N internal serial communication interface 179739cb93 RX62N internal timer modules 52c62d9d30 RX62N interrupt contorol uint cee296b1c3 target/rx: miscellaneous functions d2050c0e82 target/rx: RX disassembler 823a75d919 target/rx: CPU definition d5927fc378 target/rx: TCG helper 6c80d5cc68 target/rx: TCG Translation === OUTPUT BEGIN === 1/11 Checking commit 6c80d5cc686a (target/rx: TCG Translation) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #15: new file mode 100644 ERROR: spaces required around that '*' (ctx:WxV) #2089: FILE: target/rx/translate.c:1728: +static bool trans_FCMP_ri(DisasContext *ctx, arg_FCMP_ri *a) ^ ERROR: spaces required around that '*' (ctx:WxV) #2111: FILE: target/rx/translate.c:1750: +static bool trans_ITOF(DisasContext *ctx, arg_ITOF *a) ^ ERROR: spaces required around that '*' (ctx:WxV) #2232: FILE: target/rx/translate.c:1871: +static bool trans_BNOT_lr(DisasContext *ctx, arg_BNOT_lr *a) ^ total: 3 errors, 1 warnings, 2556 lines checked Patch 1/11 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 2/11 Checking commit d5927fc378e5 (target/rx: TCG helper) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #11: new file mode 100644 total: 0 errors, 1 warnings, 893 lines checked Patch 2/11 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 3/11 Checking commit 823a75d91989 (target/rx: CPU definition) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #11: new file mode 100644 total: 0 errors, 1 warnings, 490 lines checked Patch 3/11 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 4/11 Checking commit d2050c0e8217 (target/rx: RX disassembler) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #34: new file mode 100644 total: 0 errors, 1 warnings, 1587 lines checked Patch 4/11 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 5/11 Checking commit cee296b1c31c (target/rx: miscellaneous functions) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #11: new file mode 100644 total: 0 errors, 1 warnings, 162 lines checked Patch 5/11 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 6/11 Checking commit 52c62d9d30d9 (RX62N interrupt contorol uint) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #24: new file mode 100644 total: 0 errors, 1 warnings, 376 lines checked Patch 6/11 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 7/11 Checking commit 179739cb93ee (RX62N internal timer modules) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #30: new file mode 100644 total: 0 errors, 1 warnings, 730 lines checked Patch 7/11 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 8/11 Checking commit a6ec852164ae (RX62N internal serial communication interface) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #28: new file mode 100644 total: 0 errors, 1 warnings, 338 lines checked Patch 8/11 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 9/11 Checking commit 38c0424e72dd (RX Target hardware definition) WARNING:
[Qemu-devel] [PATCH RFC v3 00/11] Add RX archtecture support
Hello. This patch series is added Renesas RX target emulation. My git repository is bellow. git://git.pf.osdn.net/gitroot/y/ys/ysato/qemu.git Since my understanding is not enough, I want many comments to make this a good one. Thanks. Changes v2 Rewrite translate. using decodetree.py Yoshinori Sato (11): target/rx: TCG Translation target/rx: TCG helper target/rx: CPU definition target/rx: RX disassembler target/rx: miscellaneous functions RX62N interrupt contorol uint RX62N internal timer modules RX62N internal serial communication interface RX Target hardware definition Add rx-softmmu MAINTAINERS: Add RX entry. MAINTAINERS| 20 + arch_init.c|2 + configure |8 + default-configs/rx-softmmu.mak |7 + hw/char/Makefile.objs |2 +- hw/char/renesas_sci.c | 288 ++ hw/intc/Makefile.objs |1 + hw/intc/rx_icu.c | 323 ++ hw/rx/Makefile.objs|1 + hw/rx/rx62n.c | 227 hw/rx/rxqemu.c | 100 ++ hw/timer/Makefile.objs |2 + hw/timer/renesas_cmt.c | 235 + hw/timer/renesas_tmr.c | 412 include/disas/bfd.h|5 + include/hw/char/renesas_sci.h | 42 + include/hw/intc/rx_icu.h | 49 + include/hw/rx/rx.h |7 + include/hw/rx/rx62n.h | 54 + include/hw/timer/renesas_cmt.h | 33 + include/hw/timer/renesas_tmr.h | 42 + include/sysemu/arch_init.h |1 + target/rx/Makefile.objs| 11 + target/rx/cpu-qom.h| 52 + target/rx/cpu.c| 224 target/rx/cpu.h| 214 target/rx/disas.c | 1570 target/rx/gdbstub.c| 113 ++ target/rx/helper.c | 252 + target/rx/helper.h | 39 + target/rx/insns.decode | 336 ++ target/rx/monitor.c| 38 + target/rx/op_helper.c | 602 +++ target/rx/translate.c | 2220 34 files changed, 7531 insertions(+), 1 deletion(-) create mode 100644 default-configs/rx-softmmu.mak create mode 100644 hw/char/renesas_sci.c create mode 100644 hw/intc/rx_icu.c create mode 100644 hw/rx/Makefile.objs create mode 100644 hw/rx/rx62n.c create mode 100644 hw/rx/rxqemu.c create mode 100644 hw/timer/renesas_cmt.c create mode 100644 hw/timer/renesas_tmr.c create mode 100644 include/hw/char/renesas_sci.h create mode 100644 include/hw/intc/rx_icu.h create mode 100644 include/hw/rx/rx.h create mode 100644 include/hw/rx/rx62n.h create mode 100644 include/hw/timer/renesas_cmt.h create mode 100644 include/hw/timer/renesas_tmr.h create mode 100644 target/rx/Makefile.objs create mode 100644 target/rx/cpu-qom.h create mode 100644 target/rx/cpu.c create mode 100644 target/rx/cpu.h create mode 100644 target/rx/disas.c create mode 100644 target/rx/gdbstub.c create mode 100644 target/rx/helper.c create mode 100644 target/rx/helper.h create mode 100644 target/rx/insns.decode create mode 100644 target/rx/monitor.c create mode 100644 target/rx/op_helper.c create mode 100644 target/rx/translate.c -- 2.11.0
