Re: [Qemu-devel] [PATCH for-2.13] tcg: Improve TCGv_ptr support

2018-04-19 Thread Peter Maydell 
On 19 April 2018 at 11:30, Peter Maydell  wrote:
> 2018-04-17 23:26 GMT+01:00 Richard Henderson :
>> Drop TCGV_PTR_TO_NAT and TCGV_NAT_TO_PTR internal macros.
>>
>> Add tcg_temp_local_new_ptr, tcg_gen_brcondi_ptr, tcg_gen_ext_i32_ptr,
>> tcg_gen_trunc_i64_ptr, tcg_gen_extu_ptr_i64, tcg_gen_trunc_ptr_i32.
>>
>> Use inlines instead of macros where possible.
>>
>> Signed-off-by: Richard Henderson 
>> 
>>
>> These additions will be used by target/arm/translate-sve.c.
>
>> diff --git a/target/hppa/translate.c b/target/hppa/translate.c
>> index c532889b1f..cdc397308b 100644
>> --- a/target/hppa/translate.c
>> +++ b/target/hppa/translate.c
>
>> @@ -251,13 +245,7 @@
>>  #define tcg_gen_qemu_ld_reg  tcg_gen_qemu_ld_i32
>>  #define tcg_gen_qemu_st_reg  tcg_gen_qemu_st_i32
>>  #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i32
>> -#if UINTPTR_MAX == UINT32_MAX
>> -# define tcg_gen_trunc_reg_ptr(p, r) \
>> -tcg_gen_mov_i32(TCGV_PTR_TO_NAT(p), r)
>> -#else
>> -# define tcg_gen_trunc_reg_ptr(p, r) \
>> -tcg_gen_extu_i32_i64(TCGV_PTR_TO_NAT(p), r)
>> -#endif
>> +#define tcg_gen_trunc_reg_ptr   tcg_gen_ext_i32_ptr
>
> For the 64-bit host case, this used to be an unsigned
> 32->64 extension, but now it is a sign extension.

Ah, looking at the code we only use this in one place:
tcg_gen_shri_reg(tmp, base, TARGET_REGISTER_BITS - 5);
tcg_gen_andi_reg(tmp, tmp, 030);
tcg_gen_trunc_reg_ptr(ptr, tmp);

and the AND-immediate means we know the high bit of tmp
must be zero, so signed vs unsigned extension makes no difference.

So
Reviewed-by: Peter Maydell 

thanks
-- PMM

Re: [Qemu-devel] [PATCH for-2.13] tcg: Improve TCGv_ptr support

2018-04-19 Thread Peter Maydell 
2018-04-17 23:26 GMT+01:00 Richard Henderson :
> Drop TCGV_PTR_TO_NAT and TCGV_NAT_TO_PTR internal macros.
>
> Add tcg_temp_local_new_ptr, tcg_gen_brcondi_ptr, tcg_gen_ext_i32_ptr,
> tcg_gen_trunc_i64_ptr, tcg_gen_extu_ptr_i64, tcg_gen_trunc_ptr_i32.
>
> Use inlines instead of macros where possible.
>
> Signed-off-by: Richard Henderson 
> 
>
> These additions will be used by target/arm/translate-sve.c.

> diff --git a/target/hppa/translate.c b/target/hppa/translate.c
> index c532889b1f..cdc397308b 100644
> --- a/target/hppa/translate.c
> +++ b/target/hppa/translate.c

> @@ -251,13 +245,7 @@
>  #define tcg_gen_qemu_ld_reg  tcg_gen_qemu_ld_i32
>  #define tcg_gen_qemu_st_reg  tcg_gen_qemu_st_i32
>  #define tcg_gen_atomic_xchg_reg tcg_gen_atomic_xchg_i32
> -#if UINTPTR_MAX == UINT32_MAX
> -# define tcg_gen_trunc_reg_ptr(p, r) \
> -tcg_gen_mov_i32(TCGV_PTR_TO_NAT(p), r)
> -#else
> -# define tcg_gen_trunc_reg_ptr(p, r) \
> -tcg_gen_extu_i32_i64(TCGV_PTR_TO_NAT(p), r)
> -#endif
> +#define tcg_gen_trunc_reg_ptr   tcg_gen_ext_i32_ptr

For the 64-bit host case, this used to be an unsigned
32->64 extension, but now it is a sign extension.

Otherwise the patch looks good, though reading it it felt like
it was really three patches rolled into one (roughly
correpsonding to the three paragraphs in the commit message)...

thanks
-- PMM

Re: [Qemu-devel] [PATCH for-2.13] tcg: Improve TCGv_ptr support

2018-04-17 Thread no-reply 
Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20180417222635.17007-1-richard.hender...@linaro.org
Subject: [Qemu-devel] [PATCH for-2.13] tcg: Improve TCGv_ptr support

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]   
patchew/20180417222635.17007-1-richard.hender...@linaro.org -> 
patchew/20180417222635.17007-1-richard.hender...@linaro.org
Switched to a new branch 'test'
3d7fa06584 tcg: Improve TCGv_ptr support

=== OUTPUT BEGIN ===
Checking PATCH 1/1: tcg: Improve TCGv_ptr support...
ERROR: space required after that ',' (ctx:VxV)
#101: FILE: tcg/tcg-op.h:1149:
+glue(tcg_gen_ld_,PTR)((NAT)r, a, o);
 ^

ERROR: space required after that ',' (ctx:VxV)
#106: FILE: tcg/tcg-op.h:1154:
+glue(tcg_gen_discard_,PTR)((NAT)a);
  ^

ERROR: space required after that ',' (ctx:VxV)
#111: FILE: tcg/tcg-op.h:1159:
+glue(tcg_gen_add_,PTR)((NAT)r, (NAT)a, (NAT)b);
  ^

ERROR: space required after that ',' (ctx:VxV)
#116: FILE: tcg/tcg-op.h:1164:
+glue(tcg_gen_addi_,PTR)((NAT)r, (NAT)a, b);
   ^

ERROR: space required after that ',' (ctx:VxV)
#122: FILE: tcg/tcg-op.h:1170:
+glue(tcg_gen_brcondi_,PTR)(cond, (NAT)a, b, label);
  ^

total: 5 errors, 0 warnings, 305 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

=== OUTPUT END ===

Test command exited with code: 1


---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-de...@redhat.com

[Qemu-devel] [PATCH for-2.13] tcg: Improve TCGv_ptr support

2018-04-17 Thread Richard Henderson 
Drop TCGV_PTR_TO_NAT and TCGV_NAT_TO_PTR internal macros.

Add tcg_temp_local_new_ptr, tcg_gen_brcondi_ptr, tcg_gen_ext_i32_ptr,
tcg_gen_trunc_i64_ptr, tcg_gen_extu_ptr_i64, tcg_gen_trunc_ptr_i32.

Use inlines instead of macros where possible.

Signed-off-by: Richard Henderson 


These additions will be used by target/arm/translate-sve.c.


r~


 tcg/tcg-op.h| 91 +
 tcg/tcg.h   | 86 ++
 target/hppa/translate.c | 16 ++---
 tcg/tcg.c   | 31 ++---
 4 files changed, 130 insertions(+), 94 deletions(-)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 75bb55aeac..5d2c91a1b6 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1137,25 +1137,74 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg 
offset, TCGType t);
 #endif
 
 #if UINTPTR_MAX == UINT32_MAX
-# define tcg_gen_ld_ptr(R, A, O) \
-tcg_gen_ld_i32(TCGV_PTR_TO_NAT(R), (A), (O))
-# define tcg_gen_discard_ptr(A) \
-tcg_gen_discard_i32(TCGV_PTR_TO_NAT(A))
-# define tcg_gen_add_ptr(R, A, B) \
-tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), TCGV_PTR_TO_NAT(B))
-# define tcg_gen_addi_ptr(R, A, B) \
-tcg_gen_addi_i32(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), (B))
-# define tcg_gen_ext_i32_ptr(R, A) \
-tcg_gen_mov_i32(TCGV_PTR_TO_NAT(R), (A))
+# define PTR  i32
+# define NAT  TCGv_i32
 #else
-# define tcg_gen_ld_ptr(R, A, O) \
-tcg_gen_ld_i64(TCGV_PTR_TO_NAT(R), (A), (O))
-# define tcg_gen_discard_ptr(A) \
-tcg_gen_discard_i64(TCGV_PTR_TO_NAT(A))
-# define tcg_gen_add_ptr(R, A, B) \
-tcg_gen_add_i64(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), TCGV_PTR_TO_NAT(B))
-# define tcg_gen_addi_ptr(R, A, B) \
-tcg_gen_addi_i64(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), (B))
-# define tcg_gen_ext_i32_ptr(R, A) \
-tcg_gen_ext_i32_i64(TCGV_PTR_TO_NAT(R), (A))
-#endif /* UINTPTR_MAX == UINT32_MAX */
+# define PTR  i64
+# define NAT  TCGv_i64
+#endif
+
+static inline void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o)
+{
+glue(tcg_gen_ld_,PTR)((NAT)r, a, o);
+}
+
+static inline void tcg_gen_discard_ptr(TCGv_ptr a)
+{
+glue(tcg_gen_discard_,PTR)((NAT)a);
+}
+
+static inline void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b)
+{
+glue(tcg_gen_add_,PTR)((NAT)r, (NAT)a, (NAT)b);
+}
+
+static inline void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b)
+{
+glue(tcg_gen_addi_,PTR)((NAT)r, (NAT)a, b);
+}
+
+static inline void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a,
+   intptr_t b, TCGLabel *label)
+{
+glue(tcg_gen_brcondi_,PTR)(cond, (NAT)a, b, label);
+}
+
+static inline void tcg_gen_ext_i32_ptr(TCGv_ptr r, TCGv_i32 a)
+{
+#if UINTPTR_MAX == UINT32_MAX
+tcg_gen_mov_i32((NAT)r, a);
+#else
+tcg_gen_ext_i32_i64((NAT)r, a);
+#endif
+}
+
+static inline void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a)
+{
+#if UINTPTR_MAX == UINT32_MAX
+tcg_gen_extrl_i64_i32((NAT)r, a);
+#else
+tcg_gen_mov_i64((NAT)r, a);
+#endif
+}
+
+static inline void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a)
+{
+#if UINTPTR_MAX == UINT32_MAX
+tcg_gen_extu_i32_i64(r, (NAT)a);
+#else
+tcg_gen_mov_i64(r, (NAT)a);
+#endif
+}
+
+static inline void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a)
+{
+#if UINTPTR_MAX == UINT32_MAX
+tcg_gen_mov_i32(r, (NAT)a);
+#else
+tcg_gen_extrl_i64_i32(r, (NAT)a);
+#endif
+}
+
+#undef PTR
+#undef NAT
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 30896ca304..eb0d4f6ca7 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -890,15 +890,30 @@ void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t 
start, intptr_t size);
 
 TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr,
  intptr_t, const char *);
-
-TCGv_i32 tcg_temp_new_internal_i32(int temp_local);
-TCGv_i64 tcg_temp_new_internal_i64(int temp_local);
+TCGTemp *tcg_temp_new_internal(TCGType, bool);
+void tcg_temp_free_internal(TCGTemp *);
 TCGv_vec tcg_temp_new_vec(TCGType type);
 TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match);
 
-void tcg_temp_free_i32(TCGv_i32 arg);
-void tcg_temp_free_i64(TCGv_i64 arg);
-void tcg_temp_free_vec(TCGv_vec arg);
+static inline void tcg_temp_free_i32(TCGv_i32 arg)
+{
+tcg_temp_free_internal(tcgv_i32_temp(arg));
+}
+
+static inline void tcg_temp_free_i64(TCGv_i64 arg)
+{
+tcg_temp_free_internal(tcgv_i64_temp(arg));
+}
+
+static inline void tcg_temp_free_ptr(TCGv_ptr arg)
+{
+tcg_temp_free_internal(tcgv_ptr_temp(arg));
+}
+
+static inline void tcg_temp_free_vec(TCGv_vec arg)
+{
+tcg_temp_free_internal(tcgv_vec_temp(arg));
+}
 
 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
   const char *name)
@@ -909,12 +924,14 @@ static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr 
reg, intptr_t offset,
 
 static inline TCGv_i32 tcg_temp_new_i32(void)
 {
-return