Re: [Qemu-devel] [PATCH for-2.13 09/13] target/ppc: Move 1T segment and AMR options to PPCHash64Options
On Thu, Apr 05, 2018 at 02:06:19PM +0200, Greg Kurz wrote: > On Thu, 5 Apr 2018 12:14:33 +1000 > David Gibsonwrote: > > > Currently env->mmu_model is a bit of an unholy mess of an enum of distinct > > MMU types, with various flag bits as well. This makes which bits of the > > field should be compared pretty confusing. > > > > Make a start on cleaning that up by moving two of the flags bits - > > POWERPC_MMU_1TSEG and POWERPC_MMU_AMR - which are specific to the 64-bit > > hash MMU into a new flags field in PPCHash64Options structure. > > > > Signed-off-by: David Gibson > > Reviewed-by: Cédric Le Goater > > Reviewed-by: Greg Kurz > > --- > > While investigating a migration failure from an older QEMU, I realized > this patch has a problem. The *cpu->hash64_opts structure is zeroed in > kvm_fixup_page_sizes(), which has now the unwanted effect of clearing > the cpu->hash64_opts->flags as well. > > We only need to zero the segment page sizes actually. The following > fixes migration: > > @@ -442,7 +442,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu) > } > > /* Convert to QEMU form */ > -memset(cpu->hash64_opts, 0, sizeof(*cpu->hash64_opts)); > +memset(>hash64_opts->sps, 0, sizeof(cpu->hash64_opts->sps)); > > /* If we have HV KVM, we need to forbid CI large pages if our > * host page size is smaller than 64K. Ah, good catch. I mistakenly thought that kvm_fixup_page_sizes() was completely rewriting those flags as well. I've made this fix now. I'm also currently working on some other patches which amongst other things get rid of kvm_fixup_page_sizes(), because it's completely broken by design. But might as well not break things excessively in the meantime. -- David Gibson| I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson signature.asc Description: PGP signature
Re: [Qemu-devel] [PATCH for-2.13 09/13] target/ppc: Move 1T segment and AMR options to PPCHash64Options
On Thu, 5 Apr 2018 12:14:33 +1000 David Gibsonwrote: > Currently env->mmu_model is a bit of an unholy mess of an enum of distinct > MMU types, with various flag bits as well. This makes which bits of the > field should be compared pretty confusing. > > Make a start on cleaning that up by moving two of the flags bits - > POWERPC_MMU_1TSEG and POWERPC_MMU_AMR - which are specific to the 64-bit > hash MMU into a new flags field in PPCHash64Options structure. > > Signed-off-by: David Gibson > Reviewed-by: Cédric Le Goater > Reviewed-by: Greg Kurz > --- While investigating a migration failure from an older QEMU, I realized this patch has a problem. The *cpu->hash64_opts structure is zeroed in kvm_fixup_page_sizes(), which has now the unwanted effect of clearing the cpu->hash64_opts->flags as well. We only need to zero the segment page sizes actually. The following fixes migration: @@ -442,7 +442,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu) } /* Convert to QEMU form */ -memset(cpu->hash64_opts, 0, sizeof(*cpu->hash64_opts)); +memset(>hash64_opts->sps, 0, sizeof(cpu->hash64_opts->sps)); /* If we have HV KVM, we need to forbid CI large pages if our * host page size is smaller than 64K. > hw/ppc/pnv.c| 3 ++- > hw/ppc/spapr.c | 2 +- > target/ppc/cpu-qom.h| 11 +++ > target/ppc/kvm.c| 4 ++-- > target/ppc/mmu-hash64.c | 6 -- > target/ppc/mmu-hash64.h | 8 > 6 files changed, 20 insertions(+), 14 deletions(-) > > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index 5a79b24828..5905be3f71 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -36,6 +36,7 @@ > #include "monitor/monitor.h" > #include "hw/intc/intc.h" > #include "hw/ipmi/ipmi.h" > +#include "target/ppc/mmu-hash64.h" > > #include "hw/ppc/xics.h" > #include "hw/ppc/pnv_xscom.h" > @@ -187,7 +188,7 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void > *fdt) > _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); > } > > -if (env->mmu_model & POWERPC_MMU_1TSEG) { > +if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { > _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", > segs, sizeof(segs; > } > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c > index 14c31f82fa..f86cb09080 100644 > --- a/hw/ppc/spapr.c > +++ b/hw/ppc/spapr.c > @@ -557,7 +557,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void > *fdt, int offset, > _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); > } > > -if (env->mmu_model & POWERPC_MMU_1TSEG) { > +if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { > _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", >segs, sizeof(segs; > } > diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h > index 3e5ef7375f..2bd58b2a84 100644 > --- a/target/ppc/cpu-qom.h > +++ b/target/ppc/cpu-qom.h > @@ -68,22 +68,17 @@ enum powerpc_mmu_t { > /* PowerPC 601 MMU model (specific BATs format)*/ > POWERPC_MMU_601= 0x000A, > #define POWERPC_MMU_64 0x0001 > -#define POWERPC_MMU_1TSEG0x0002 > -#define POWERPC_MMU_AMR 0x0004 > #define POWERPC_MMU_V3 0x0010 /* ISA V3.00 MMU Support */ > /* 64 bits PowerPC MMU */ > POWERPC_MMU_64B= POWERPC_MMU_64 | 0x0001, > /* Architecture 2.03 and later (has LPCR) */ > POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x0002, > /* Architecture 2.06 variant */ > -POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG > - | POWERPC_MMU_AMR | 0x0003, > +POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x0003, > /* Architecture 2.07 variant */ > -POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG > - | POWERPC_MMU_AMR | 0x0004, > +POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x0004, > /* Architecture 3.00 variant */ > -POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG > - | POWERPC_MMU_AMR | POWERPC_MMU_V3 > +POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_V3 > | 0x0005, > }; > #define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0x)) > diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c > index bc6d0a8314..22487cef06 100644 > --- a/target/ppc/kvm.c > +++ b/target/ppc/kvm.c > @@ -302,7 +302,7 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu, > /* HV KVM has backing store size restrictions */ > info->flags = KVM_PPC_PAGE_SIZES_REAL; > > -if (env->mmu_model & POWERPC_MMU_1TSEG) { > +if (ppc_hash64_has(cpu,
[Qemu-devel] [PATCH for-2.13 09/13] target/ppc: Move 1T segment and AMR options to PPCHash64Options
Currently env->mmu_model is a bit of an unholy mess of an enum of distinct MMU types, with various flag bits as well. This makes which bits of the field should be compared pretty confusing. Make a start on cleaning that up by moving two of the flags bits - POWERPC_MMU_1TSEG and POWERPC_MMU_AMR - which are specific to the 64-bit hash MMU into a new flags field in PPCHash64Options structure. Signed-off-by: David GibsonReviewed-by: Cédric Le Goater Reviewed-by: Greg Kurz --- hw/ppc/pnv.c| 3 ++- hw/ppc/spapr.c | 2 +- target/ppc/cpu-qom.h| 11 +++ target/ppc/kvm.c| 4 ++-- target/ppc/mmu-hash64.c | 6 -- target/ppc/mmu-hash64.h | 8 6 files changed, 20 insertions(+), 14 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 5a79b24828..5905be3f71 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -36,6 +36,7 @@ #include "monitor/monitor.h" #include "hw/intc/intc.h" #include "hw/ipmi/ipmi.h" +#include "target/ppc/mmu-hash64.h" #include "hw/ppc/xics.h" #include "hw/ppc/pnv_xscom.h" @@ -187,7 +188,7 @@ static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); } -if (env->mmu_model & POWERPC_MMU_1TSEG) { +if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", segs, sizeof(segs; } diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 14c31f82fa..f86cb09080 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -557,7 +557,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); } -if (env->mmu_model & POWERPC_MMU_1TSEG) { +if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", segs, sizeof(segs; } diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 3e5ef7375f..2bd58b2a84 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -68,22 +68,17 @@ enum powerpc_mmu_t { /* PowerPC 601 MMU model (specific BATs format)*/ POWERPC_MMU_601= 0x000A, #define POWERPC_MMU_64 0x0001 -#define POWERPC_MMU_1TSEG0x0002 -#define POWERPC_MMU_AMR 0x0004 #define POWERPC_MMU_V3 0x0010 /* ISA V3.00 MMU Support */ /* 64 bits PowerPC MMU */ POWERPC_MMU_64B= POWERPC_MMU_64 | 0x0001, /* Architecture 2.03 and later (has LPCR) */ POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x0002, /* Architecture 2.06 variant */ -POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG - | POWERPC_MMU_AMR | 0x0003, +POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x0003, /* Architecture 2.07 variant */ -POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG - | POWERPC_MMU_AMR | 0x0004, +POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x0004, /* Architecture 3.00 variant */ -POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG - | POWERPC_MMU_AMR | POWERPC_MMU_V3 +POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_V3 | 0x0005, }; #define POWERPC_MMU_VER(x) ((x) & (POWERPC_MMU_64 | 0x)) diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index bc6d0a8314..22487cef06 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -302,7 +302,7 @@ static void kvm_get_fallback_smmu_info(PowerPCCPU *cpu, /* HV KVM has backing store size restrictions */ info->flags = KVM_PPC_PAGE_SIZES_REAL; -if (env->mmu_model & POWERPC_MMU_1TSEG) { +if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { info->flags |= KVM_PPC_1T_SEGMENTS; } @@ -482,7 +482,7 @@ static void kvm_fixup_page_sizes(PowerPCCPU *cpu) } env->slb_nr = smmu_info.slb_size; if (!(smmu_info.flags & KVM_PPC_1T_SEGMENTS)) { -env->mmu_model &= ~POWERPC_MMU_1TSEG; +cpu->hash64_opts->flags &= ~PPC_HASH64_1TSEG; } } diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 2809c31170..c9ee55e1ea 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -160,7 +160,7 @@ int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, if (vsid & (SLB_VSID_B & ~SLB_VSID_B_1T)) { return -1; /* Bad segment size */ } -if ((vsid & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) { +if ((vsid & SLB_VSID_B) && !(ppc_hash64_has(cpu, PPC_HASH64_1TSEG))) { return -1; /* 1T segment on MMU that doesn't support it */ } @@ -369,7 +369,7 @@ static int