Re: [Qemu-devel] [PATCH for 4.0 v1 5/5] riscv: plic: Log guest errors

[Philippe Mathieu-Daudé]

Le jeu. 21 mars 2019 02:00, Alistair Francis  a
écrit :

> Instead of using error_report() to print guest errors let's use
> qemu_log_mask(LOG_GUEST_ERROR,...) to log the error.
>
> Signed-off-by: Alistair Francis 
> ---
>  hw/riscv/sifive_plic.c | 12 +---
>  1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
> index 70a85cd075..7f373d6c9d 100644
> --- a/hw/riscv/sifive_plic.c
> +++ b/hw/riscv/sifive_plic.c
> @@ -262,7 +262,9 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr
> addr, unsigned size)
>  }
>
>  err:
> -error_report("plic: invalid register read: %08x", (uint32_t)addr);
> +qemu_log_mask(LOG_GUEST_ERROR,
> +  "%s: Invalid register read 0x%" HWADDR_PRIx "\n",
> +  __func__, addr);
>  return 0;
>  }
>
> @@ -289,7 +291,9 @@ static void sifive_plic_write(void *opaque, hwaddr
> addr, uint64_t value,
>  } else if (addr >= plic->pending_base && /* 1 bit per source */
> addr < plic->pending_base + (plic->num_sources >> 3))
>  {
> -error_report("plic: invalid pending write: %08x", (uint32_t)addr);
> +qemu_log_mask(LOG_GUEST_ERROR,
> +  "%s: invalid pending write: 0x%" HWADDR_PRIx "",
> +  __func__, addr);
>  return;
>  } else if (addr >= plic->enable_base && /* 1 bit per source */
>  addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
> @@ -339,7 +343,9 @@ static void sifive_plic_write(void *opaque, hwaddr
> addr, uint64_t value,
>  }
>
>  err:
> -error_report("plic: invalid register write: %08x", (uint32_t)addr);
> +qemu_log_mask(LOG_GUEST_ERROR,
> +  "%s: Invalid register write 0x%" HWADDR_PRIx "\n",
> +  __func__, addr);
>  }
>
>  static const MemoryRegionOps sifive_plic_ops = {
> --
> 2.21.0
>

Reviewed-by: Philippe Mathieu-Daudé 

>

[Qemu-devel] [PATCH for 4.0 v1 5/5] riscv: plic: Log guest errors

[Alistair Francis]

Instead of using error_report() to print guest errors let's use
qemu_log_mask(LOG_GUEST_ERROR,...) to log the error.

Signed-off-by: Alistair Francis 
---
 hw/riscv/sifive_plic.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c
index 70a85cd075..7f373d6c9d 100644
--- a/hw/riscv/sifive_plic.c
+++ b/hw/riscv/sifive_plic.c
@@ -262,7 +262,9 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, 
unsigned size)
 }
 
 err:
-error_report("plic: invalid register read: %08x", (uint32_t)addr);
+qemu_log_mask(LOG_GUEST_ERROR,
+  "%s: Invalid register read 0x%" HWADDR_PRIx "\n",
+  __func__, addr);
 return 0;
 }
 
@@ -289,7 +291,9 @@ static void sifive_plic_write(void *opaque, hwaddr addr, 
uint64_t value,
 } else if (addr >= plic->pending_base && /* 1 bit per source */
addr < plic->pending_base + (plic->num_sources >> 3))
 {
-error_report("plic: invalid pending write: %08x", (uint32_t)addr);
+qemu_log_mask(LOG_GUEST_ERROR,
+  "%s: invalid pending write: 0x%" HWADDR_PRIx "",
+  __func__, addr);
 return;
 } else if (addr >= plic->enable_base && /* 1 bit per source */
 addr < plic->enable_base + plic->num_addrs * plic->enable_stride)
@@ -339,7 +343,9 @@ static void sifive_plic_write(void *opaque, hwaddr addr, 
uint64_t value,
 }
 
 err:
-error_report("plic: invalid register write: %08x", (uint32_t)addr);
+qemu_log_mask(LOG_GUEST_ERROR,
+  "%s: Invalid register write 0x%" HWADDR_PRIx "\n",
+  __func__, addr);
 }
 
 static const MemoryRegionOps sifive_plic_ops = {
-- 
2.21.0