Re: [Qemu-devel] [PATCH risu] ppc64: Fix patterns for rotate doubleword instructions

2017-05-30 Thread G 3 


On May 30, 2017, at 8:01 AM, Peter Maydell wrote:


On 25 May 2017 at 21:05,   wrote:

What do you think about sharing the same ppc64.risu file to ppc
and ppc64/ppc64le. Then, instead of:

 PPC64LE 0...

we'd have:

 PPC 0...

So, specific instructions would be:

 PPC64LE 0...
 PPC64 0...
 PPC32 0...

It will allow users to select the arch by using patterns like: ./ 
risugen

--pattern "PPC64*", or --pattern "PPC32*".


I think we should aim to share the files, but that we should
have a better mechanism than just a convention on the pattern
name (which is easy to make mistakes with and also makes it
harder to use the --pattern argument for the purpose it was
intended for, since you have to combine your desired pattern
with the pattern to select the right bit of the instruction set).
This isn't limited to PPC either -- for ARM we'd like to be
able to mark instructions as ARMv7/ARMv8/present in some
optional instruction set extension, etc.


Do you want to add an architecture option?

--pattern 'F.*' --arch PPC32

In this example only the instructions that begin with the letter F  
and have PPC32 as an encodingname are used.




We could perhaps do that with an optional field in the
lines in the risu file to mark what part of the instruction
set they're in, and a command line argument to select the
instruction set variant(s) desired.


I thought we already had this feature.

From the readme file:

insnname encodingname bitfield ... [ [ !blockname ] { blocktext } ]

Isn't the encodingname field the field we could use to select the  
variant we want?




Another possible approach would be to have the PPC32 insns
in their own file, and some sort of #include directive to
pull them into the PPC64 file.

This is all "adding extra features to risu", though, so I
don't insist it be done.


The #include directive does sound interesting but if you really want  
one PowerPC risu file then Jose's way would be the way to go. Risu as  
it is can handle this.

Re: [Qemu-devel] [PATCH risu] ppc64: Fix patterns for rotate doubleword instructions

2017-05-30 Thread Peter Maydell 
On 25 May 2017 at 21:05,   wrote:
> What do you think about sharing the same ppc64.risu file to ppc
> and ppc64/ppc64le. Then, instead of:
>
>  PPC64LE 0...
>
> we'd have:
>
>  PPC 0...
>
> So, specific instructions would be:
>
>  PPC64LE 0...
>  PPC64 0...
>  PPC32 0...
>
> It will allow users to select the arch by using patterns like: ./risugen
> --pattern "PPC64*", or --pattern "PPC32*".

I think we should aim to share the files, but that we should
have a better mechanism than just a convention on the pattern
name (which is easy to make mistakes with and also makes it
harder to use the --pattern argument for the purpose it was
intended for, since you have to combine your desired pattern
with the pattern to select the right bit of the instruction set).
This isn't limited to PPC either -- for ARM we'd like to be
able to mark instructions as ARMv7/ARMv8/present in some
optional instruction set extension, etc.

We could perhaps do that with an optional field in the
lines in the risu file to mark what part of the instruction
set they're in, and a command line argument to select the
instruction set variant(s) desired.

Another possible approach would be to have the PPC32 insns
in their own file, and some sort of #include directive to
pull them into the PPC64 file.

This is all "adding extra features to risu", though, so I
don't insist it be done.

thanks
-- PMM

Re: [Qemu-devel] [PATCH risu] ppc64: Fix patterns for rotate doubleword instructions

2017-05-25 Thread Programmingkid 

On May 25, 2017, at 4:05 PM, jos...@linux.vnet.ibm.com wrote:

> On Tue, May 23, 2017 at 11:33:03PM -0300, jos...@linux.vnet.ibm.com wrote:
>> On Tue, May 23, 2017 at 11:47:30AM +0530, Nikunj A Dadhania wrote:
>>> G 3  writes:
>>> 
 On May 22, 2017, at 4:32 AM, qemu-devel-requ...@nongnu.org wrote:
 
 Hello I have also done some work risu. My patches add ppc32 support.  
 Well my patches were made to work with Mac OS X but they are required  
 to work with Linux. Do you think you could help port these patches to  
 Linux?
>>> 
>>> Ziviani did the ppc64 work, lets see if he can spare some time.
>>> 
>>> The patches haven't come right on the mailing list, its tedious to pull
>>> them. Please resend them with git send-mail.
>>> 
>> 
>> Hey, sure I can help. I'll take a look on them.
>> 
 
 ppc.risu:
 https://patchwork.kernel.org/patch/9697489/
> 
> Hi John,
> 
> What do you think about sharing the same ppc64.risu file to ppc and 
> ppc64/ppc64le. Then, instead of:
> 
>  PPC64LE 0...
> 
> we'd have:
> 
>  PPC 0...
> 
> So, specific instructions would be:
> 
>  PPC64LE 0...
>  PPC64 0...
>  PPC32 0...
> 
> It will allow users to select the arch by using patterns like: ./risugen
> --pattern "PPC64*", or --pattern "PPC32*".
> 
> Finally, we could rename ppc64.risu to powerpc.risu :).
> 
> What do you think?
> 
> Thanks

I think have two separate files is best. Making the .out file becomes so much 
easier. There is no worry for PPC64 instructions being included accidentally in 
a PPC test. Also generating the .out file wouldn't require the --pattern 
option. There is also the possibility of instructions acting in a different 
manner between the two architectures. The ADD instruction may work without 
problems but instructions that do need to know the bit size of the processor  
like CMP will not be easy to implement on both architectures. 

Thank you

Re: [Qemu-devel] [PATCH risu] ppc64: Fix patterns for rotate doubleword instructions

2017-05-25 Thread joserz 
On Tue, May 23, 2017 at 11:33:03PM -0300, jos...@linux.vnet.ibm.com wrote:
> On Tue, May 23, 2017 at 11:47:30AM +0530, Nikunj A Dadhania wrote:
> > G 3  writes:
> > 
> > > On May 22, 2017, at 4:32 AM, qemu-devel-requ...@nongnu.org wrote:
> > >
> > > Hello I have also done some work risu. My patches add ppc32 support.  
> > > Well my patches were made to work with Mac OS X but they are required  
> > > to work with Linux. Do you think you could help port these patches to  
> > > Linux?
> > 
> > Ziviani did the ppc64 work, lets see if he can spare some time.
> > 
> > The patches haven't come right on the mailing list, its tedious to pull
> > them. Please resend them with git send-mail.
> > 
> 
> Hey, sure I can help. I'll take a look on them.
> 
> > >
> > > ppc.risu:
> > > https://patchwork.kernel.org/patch/9697489/

Hi John,

What do you think about sharing the same ppc64.risu file to ppc and 
ppc64/ppc64le. Then, instead of:

 PPC64LE 0...

we'd have:

 PPC 0...

So, specific instructions would be:

 PPC64LE 0...
 PPC64 0...
 PPC32 0...

It will allow users to select the arch by using patterns like: ./risugen
--pattern "PPC64*", or --pattern "PPC32*".

Finally, we could rename ppc64.risu to powerpc.risu :).

What do you think?

Thanks

Re: [Qemu-devel] [PATCH risu] ppc64: Fix patterns for rotate doubleword instructions

2017-05-23 Thread joserz 
On Tue, May 23, 2017 at 11:47:30AM +0530, Nikunj A Dadhania wrote:
> G 3  writes:
> 
> > On May 22, 2017, at 4:32 AM, qemu-devel-requ...@nongnu.org wrote:
> >
> > Hello I have also done some work risu. My patches add ppc32 support.  
> > Well my patches were made to work with Mac OS X but they are required  
> > to work with Linux. Do you think you could help port these patches to  
> > Linux?
> 
> Ziviani did the ppc64 work, lets see if he can spare some time.
> 
> The patches haven't come right on the mailing list, its tedious to pull
> them. Please resend them with git send-mail.
> 

Hey, sure I can help. I'll take a look on them.

> >
> > ppc.risu:
> > https://patchwork.kernel.org/patch/9697489/
> >
> > risu_ppc.c:
> > https://patchwork.kernel.org/patch/9697491/
> >
> > risu_reginfo_ppc.c:
> > https://patchwork.kernel.org/patch/9697493/
> >
> > risu_reginfo_ppc.h:
> > https://patchwork.kernel.org/patch/9697495/
> >
> > risugen_ppc.pm:
> > https://patchwork.kernel.org/patch/9697497/
> >
> > Add ppc support to configure:
> > https://patchwork.kernel.org/patch/9697499/
> >
> > Add verbose option:
> > https://patchwork.kernel.org/patch/9697501/
> >
> > Add end of test message:
> > https://patchwork.kernel.org/patch/9697503/
> >
> > Add more descriptive comment for mismatch or end of test condition:
> > https://patchwork.kernel.org/patch/9697505/
> 
> Regards
> Nikunj
>

Re: [Qemu-devel] [PATCH risu] ppc64: Fix patterns for rotate doubleword instructions

2017-05-23 Thread Nikunj A Dadhania 
G 3  writes:

> On May 22, 2017, at 4:32 AM, qemu-devel-requ...@nongnu.org wrote:
>
> Hello I have also done some work risu. My patches add ppc32 support.  
> Well my patches were made to work with Mac OS X but they are required  
> to work with Linux. Do you think you could help port these patches to  
> Linux?

Ziviani did the ppc64 work, lets see if he can spare some time.

The patches haven't come right on the mailing list, its tedious to pull
them. Please resend them with git send-mail.

>
> ppc.risu:
> https://patchwork.kernel.org/patch/9697489/
>
> risu_ppc.c:
> https://patchwork.kernel.org/patch/9697491/
>
> risu_reginfo_ppc.c:
> https://patchwork.kernel.org/patch/9697493/
>
> risu_reginfo_ppc.h:
> https://patchwork.kernel.org/patch/9697495/
>
> risugen_ppc.pm:
> https://patchwork.kernel.org/patch/9697497/
>
> Add ppc support to configure:
> https://patchwork.kernel.org/patch/9697499/
>
> Add verbose option:
> https://patchwork.kernel.org/patch/9697501/
>
> Add end of test message:
> https://patchwork.kernel.org/patch/9697503/
>
> Add more descriptive comment for mismatch or end of test condition:
> https://patchwork.kernel.org/patch/9697505/

Regards
Nikunj

Re: [Qemu-devel] [PATCH risu] ppc64: Fix patterns for rotate doubleword instructions

2017-05-22 Thread Sandipan Das 
On Monday 22 May 2017 12:33 PM, Nikunj A Dadhania wrote:
> Sandipan Das  writes:
> 
>> The patterns for the following instructions are fixed:
>>  * Rotate Left Doubleword then Clear Right (rldcr[.])
>>  * Rotate Left Doubleword Immediate then Clear Right (rldicr[.])
>>  * Rotate Left Doubleword Immediate then Mask Insert (rldimi[.])
>>
>> Signed-off-by: Sandipan Das 
>> ---
>>  ppc64.risu | 10 +-
>>  1 file changed, 5 insertions(+), 5 deletions(-)
>>
>> diff --git a/ppc64.risu b/ppc64.risu
>> index 28df9da..0f29248 100644
>> --- a/ppc64.risu
>> +++ b/ppc64.risu
>> @@ -1451,7 +1451,7 @@ RLDCLd PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10001 \
>>  !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 
>> && $rb != 13; }
>>
>>  # format:MDS book:I page:103 PPC SR rldcr Rotate Left Dword then Clear Right
>> -RLCDR PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10010 \
>> +RLDCR PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10010 \
>>  !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 
>> && $rb != 13; }
>>  # format:MDS book:I page:103 PPC SR rldcr Rotate Left Dword then Clear Right
>>  RLDCRd PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10011 \
>> @@ -1472,17 +1472,17 @@ RLDICLd PPC64LE 00 rs:5 ra:5 sh:5 mb:6 000 sha:1 
>> 1 \
>>  !constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
>>
>>  # format:MD book:I page:105 PPC SR rldicr[.] Rotate Left Dword Immediate 
>> then Clear Right
>> -RLDICR PPC64LE 00 rs:5 ra:5 rb:5 me:6 00010 \
>> +RLDICR PPC64LE 00 rs:5 ra:5 rb:5 me:6 001 sha:1 0 \
> 
>RLDICR PPC64LE 00 rs:5 ra:5 sh:5 me:6 001 sha:1 0
> 
> Also "rb:5" be changed as "sh:5"?

Yes, I missed that.

> 
>>  !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 
>> && $rb != 13; }
>>  # format:MD book:I page:105 PPC SR rldicr[.] Rotate Left Dword Immediate 
>> then Clear Right
>> -RLDICRd PPC64LE 00 rs:5 ra:5 rb:5 me:6 00011 \
>> +RLDICRd PPC64LE 00 rs:5 ra:5 rb:5 me:6 001 sha:1 1 \
> 
>RLDICRd PPC64LE 00 rs:5 ra:5 sh:5 me:6 001 sha:1 0
> 
> 
>>  !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 
>> && $rb != 13; }
>>
>>  # format:MD book:I page:105 PPC SR rldimi[.] Rotate Left Dword Immediate 
>> then Mask Insert
>> -RLDIMI PPC64LE 00 rs:5 ra:5 rb:5 me:6 00110 \
>> +RLDIMI PPC64LE 00 rs:5 ra:5 rb:5 me:6 011 sha:1 0 \
> 
>RLDIMI PPC64LE 00 rs:5 ra:5 sh:5 me:6 011 sha:1 0
> 
> 
>>  !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 
>> && $rb != 13; }
>>  # format:MD book:I page:105 PPC SR rldimi[.] Rotate Left Dword Immediate 
>> then Mask Insert
>> -RLDIMId PPC64LE 00 rs:5 ra:5 rb:5 me:6 00111 \
>> +RLDIMId PPC64LE 00 rs:5 ra:5 rb:5 me:6 011 sha:1 1 \
> 
>RLDIMId PPC64LE 00 rs:5 ra:5 sh:5 me:6 011 sha:1 1
> 
>>  !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 
>> && $rb != 13; }
>>
>>  # format:M book:I page:102 v:P1 SR rlwimi[.] Rotate Left Word Immediate 
>> then Mask Insert
>> -- 
>> 2.7.4
> 
> Regards,
> Nikunj
> 

With Regards,
Sandipan

[Qemu-devel] [PATCH risu] ppc64: Fix patterns for rotate doubleword instructions

2017-05-22 Thread Sandipan Das 
The patterns for the following instructions are fixed:
 * Rotate Left Doubleword then Clear Right (rldcr[.])
 * Rotate Left Doubleword Immediate then Clear Right (rldicr[.])
 * Rotate Left Doubleword Immediate then Mask Insert (rldimi[.])

Signed-off-by: Sandipan Das 
---
 ppc64.risu | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/ppc64.risu b/ppc64.risu
index 28df9da..0f29248 100644
--- a/ppc64.risu
+++ b/ppc64.risu
@@ -1451,7 +1451,7 @@ RLDCLd PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10001 \
 !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && 
$rb != 13; }
 
 # format:MDS book:I page:103 PPC SR rldcr Rotate Left Dword then Clear Right
-RLCDR PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10010 \
+RLDCR PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10010 \
 !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && 
$rb != 13; }
 # format:MDS book:I page:103 PPC SR rldcr Rotate Left Dword then Clear Right
 RLDCRd PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10011 \
@@ -1472,17 +1472,17 @@ RLDICLd PPC64LE 00 rs:5 ra:5 sh:5 mb:6 000 sha:1 1 \
 !constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
 
 # format:MD book:I page:105 PPC SR rldicr[.] Rotate Left Dword Immediate then 
Clear Right
-RLDICR PPC64LE 00 rs:5 ra:5 rb:5 me:6 00010 \
+RLDICR PPC64LE 00 rs:5 ra:5 rb:5 me:6 001 sha:1 0 \
 !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && 
$rb != 13; }
 # format:MD book:I page:105 PPC SR rldicr[.] Rotate Left Dword Immediate then 
Clear Right
-RLDICRd PPC64LE 00 rs:5 ra:5 rb:5 me:6 00011 \
+RLDICRd PPC64LE 00 rs:5 ra:5 rb:5 me:6 001 sha:1 1 \
 !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && 
$rb != 13; }
 
 # format:MD book:I page:105 PPC SR rldimi[.] Rotate Left Dword Immediate then 
Mask Insert
-RLDIMI PPC64LE 00 rs:5 ra:5 rb:5 me:6 00110 \
+RLDIMI PPC64LE 00 rs:5 ra:5 rb:5 me:6 011 sha:1 0 \
 !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && 
$rb != 13; }
 # format:MD book:I page:105 PPC SR rldimi[.] Rotate Left Dword Immediate then 
Mask Insert
-RLDIMId PPC64LE 00 rs:5 ra:5 rb:5 me:6 00111 \
+RLDIMId PPC64LE 00 rs:5 ra:5 rb:5 me:6 011 sha:1 1 \
 !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && 
$rb != 13; }
 
 # format:M book:I page:102 v:P1 SR rlwimi[.] Rotate Left Word Immediate then 
Mask Insert
-- 
2.7.4

Re: [Qemu-devel] [PATCH risu] ppc64: Fix patterns for rotate doubleword instructions

2017-05-22 Thread G 3 


On May 22, 2017, at 4:32 AM, qemu-devel-requ...@nongnu.org wrote:


Message: 2
Date: Mon, 22 May 2017 12:33:29 +0530
From: Nikunj A Dadhania <nik...@linux.vnet.ibm.com>
To: Sandipan Das <sandipandas1...@gmail.com>
Cc: qemu-devel@nongnu.org, peter.mayd...@linaro.org,
jos...@linux.vnet.ibm.com
Subject: Re: [Qemu-devel] [PATCH risu] ppc64: Fix patterns for rotate
    doubleword instructions
Message-ID:
	<87a865nzjy.fsf@abhimanyu.i-did-not-set--mail-host-address--so- 
tickle-me>


Content-Type: text/plain

Sandipan Das <sandipandas1...@gmail.com> writes:


The patterns for the following instructions are fixed:
 * Rotate Left Doubleword then Clear Right (rldcr[.])
 * Rotate Left Doubleword Immediate then Clear Right (rldicr[.])
 * Rotate Left Doubleword Immediate then Mask Insert (rldimi[.])

Signed-off-by: Sandipan Das <sandipandas1...@gmail.com>
---
 ppc64.risu | 10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/ppc64.risu b/ppc64.risu
index 28df9da..0f29248 100644
--- a/ppc64.risu
+++ b/ppc64.risu
@@ -1451,7 +1451,7 @@ RLDCLd PPC64LE 00 rs:5 ra:5 rb:5 mb:6  
10001 \
 !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 &&  
$ra != 13 && $rb != 13; }


 # format:MDS book:I page:103 PPC SR rldcr Rotate Left Dword then  
Clear Right

-RLCDR PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10010 \
+RLDCR PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10010 \
 !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 &&  
$ra != 13 && $rb != 13; }
 # format:MDS book:I page:103 PPC SR rldcr Rotate Left Dword then  
Clear Right

 RLDCRd PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10011 \
@@ -1472,17 +1472,17 @@ RLDICLd PPC64LE 00 rs:5 ra:5 sh:5 mb:6  
000 sha:1 1 \

 !constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }

 # format:MD book:I page:105 PPC SR rldicr[.] Rotate Left Dword  
Immediate then Clear Right

-RLDICR PPC64LE 00 rs:5 ra:5 rb:5 me:6 00010 \
+RLDICR PPC64LE 00 rs:5 ra:5 rb:5 me:6 001 sha:1 0 \


   RLDICR PPC64LE 00 rs:5 ra:5 sh:5 me:6 001 sha:1 0

Also "rb:5" be changed as "sh:5"?

 !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 &&  
$ra != 13 && $rb != 13; }
 # format:MD book:I page:105 PPC SR rldicr[.] Rotate Left Dword  
Immediate then Clear Right

-RLDICRd PPC64LE 00 rs:5 ra:5 rb:5 me:6 00011 \
+RLDICRd PPC64LE 00 rs:5 ra:5 rb:5 me:6 001 sha:1 1 \


   RLDICRd PPC64LE 00 rs:5 ra:5 sh:5 me:6 001 sha:1 0


 !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 &&  
$ra != 13 && $rb != 13; }


 # format:MD book:I page:105 PPC SR rldimi[.] Rotate Left Dword  
Immediate then Mask Insert

-RLDIMI PPC64LE 00 rs:5 ra:5 rb:5 me:6 00110 \
+RLDIMI PPC64LE 00 rs:5 ra:5 rb:5 me:6 011 sha:1 0 \


   RLDIMI PPC64LE 00 rs:5 ra:5 sh:5 me:6 011 sha:1 0


 !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 &&  
$ra != 13 && $rb != 13; }
 # format:MD book:I page:105 PPC SR rldimi[.] Rotate Left Dword  
Immediate then Mask Insert

-RLDIMId PPC64LE 00 rs:5 ra:5 rb:5 me:6 00111 \
+RLDIMId PPC64LE 00 rs:5 ra:5 rb:5 me:6 011 sha:1 1 \


   RLDIMId PPC64LE 00 rs:5 ra:5 sh:5 me:6 011 sha:1 1

 !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 &&  
$ra != 13 && $rb != 13; }


 # format:M book:I page:102 v:P1 SR rlwimi[.] Rotate Left Word  
Immediate then Mask Insert

--
2.7.4


Regards,
Nikunj


Hello I have also done some work risu. My patches add ppc32 support.  
Well my patches were made to work with Mac OS X but they are required  
to work with Linux. Do you think you could help port these patches to  
Linux?


ppc.risu:
https://patchwork.kernel.org/patch/9697489/

risu_ppc.c:
https://patchwork.kernel.org/patch/9697491/

risu_reginfo_ppc.c:
https://patchwork.kernel.org/patch/9697493/

risu_reginfo_ppc.h:
https://patchwork.kernel.org/patch/9697495/

risugen_ppc.pm:
https://patchwork.kernel.org/patch/9697497/

Add ppc support to configure:
https://patchwork.kernel.org/patch/9697499/

Add verbose option:
https://patchwork.kernel.org/patch/9697501/

Add end of test message:
https://patchwork.kernel.org/patch/9697503/

Add more descriptive comment for mismatch or end of test condition:
https://patchwork.kernel.org/patch/9697505/

Re: [Qemu-devel] [PATCH risu] ppc64: Fix patterns for rotate doubleword instructions

2017-05-22 Thread Nikunj A Dadhania 
Sandipan Das  writes:

> The patterns for the following instructions are fixed:
>  * Rotate Left Doubleword then Clear Right (rldcr[.])
>  * Rotate Left Doubleword Immediate then Clear Right (rldicr[.])
>  * Rotate Left Doubleword Immediate then Mask Insert (rldimi[.])
>
> Signed-off-by: Sandipan Das 
> ---
>  ppc64.risu | 10 +-
>  1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/ppc64.risu b/ppc64.risu
> index 28df9da..0f29248 100644
> --- a/ppc64.risu
> +++ b/ppc64.risu
> @@ -1451,7 +1451,7 @@ RLDCLd PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10001 \
>  !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && 
> $rb != 13; }
>
>  # format:MDS book:I page:103 PPC SR rldcr Rotate Left Dword then Clear Right
> -RLCDR PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10010 \
> +RLDCR PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10010 \
>  !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && 
> $rb != 13; }
>  # format:MDS book:I page:103 PPC SR rldcr Rotate Left Dword then Clear Right
>  RLDCRd PPC64LE 00 rs:5 ra:5 rb:5 mb:6 10011 \
> @@ -1472,17 +1472,17 @@ RLDICLd PPC64LE 00 rs:5 ra:5 sh:5 mb:6 000 sha:1 
> 1 \
>  !constraints { $rs != 1 && $ra != 1 && $rs != 13 && $ra != 13; }
>
>  # format:MD book:I page:105 PPC SR rldicr[.] Rotate Left Dword Immediate 
> then Clear Right
> -RLDICR PPC64LE 00 rs:5 ra:5 rb:5 me:6 00010 \
> +RLDICR PPC64LE 00 rs:5 ra:5 rb:5 me:6 001 sha:1 0 \

   RLDICR PPC64LE 00 rs:5 ra:5 sh:5 me:6 001 sha:1 0

Also "rb:5" be changed as "sh:5"?

>  !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && 
> $rb != 13; }
>  # format:MD book:I page:105 PPC SR rldicr[.] Rotate Left Dword Immediate 
> then Clear Right
> -RLDICRd PPC64LE 00 rs:5 ra:5 rb:5 me:6 00011 \
> +RLDICRd PPC64LE 00 rs:5 ra:5 rb:5 me:6 001 sha:1 1 \

   RLDICRd PPC64LE 00 rs:5 ra:5 sh:5 me:6 001 sha:1 0


>  !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && 
> $rb != 13; }
>
>  # format:MD book:I page:105 PPC SR rldimi[.] Rotate Left Dword Immediate 
> then Mask Insert
> -RLDIMI PPC64LE 00 rs:5 ra:5 rb:5 me:6 00110 \
> +RLDIMI PPC64LE 00 rs:5 ra:5 rb:5 me:6 011 sha:1 0 \

   RLDIMI PPC64LE 00 rs:5 ra:5 sh:5 me:6 011 sha:1 0


>  !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && 
> $rb != 13; }
>  # format:MD book:I page:105 PPC SR rldimi[.] Rotate Left Dword Immediate 
> then Mask Insert
> -RLDIMId PPC64LE 00 rs:5 ra:5 rb:5 me:6 00111 \
> +RLDIMId PPC64LE 00 rs:5 ra:5 rb:5 me:6 011 sha:1 1 \

   RLDIMId PPC64LE 00 rs:5 ra:5 sh:5 me:6 011 sha:1 1

>  !constraints { $rs != 1 && $ra != 1 && $rb != 1 && $rs != 13 && $ra != 13 && 
> $rb != 13; }
>
>  # format:M book:I page:102 v:P1 SR rlwimi[.] Rotate Left Word Immediate then 
> Mask Insert
> -- 
> 2.7.4

Regards,
Nikunj