Re: [Qemu-devel] [PATCH v10 00/15] QEMU OpenRISC support
On Fri, Jul 20, 2012 at 7:50 AM, Jia Liu pro...@gmail.com wrote: This is the OpenCores OpenRISC 1200 support for QEMU. Full implementation of the system-model and linux-user-model support. OpenRISC 1200 is a OpenCores open source CPU, its architecture manual can be found at http://opencores.org/svnget,or1k?file=/trunk/docs/openrisc_arch.pdf A OpenRISC Linux kernel contain initramfs for qemu-system-or32 testing can be found at https://docs.google.com/file/d/0BxeTrz3x0CBLSjR3Sk5Vd3h1eDA/edit?pli=1 A OpenRISC hello-world program for qemu-or32 testing can be found at https://docs.google.com/file/d/0BxeTrz3x0CBLN3RSWUFNYktrU2M/edit?pli=1 Signed-off-by: Jia Liu pro...@gmail.com Thanks, applied all. --- Version History: v10: Addressed Peter's review comments: - replace field() with extract32() using for decode Addressed Max's review comments: - reimplement l.ff1 and l.fl1 by using ctz32() and clz32() - make helper func mul32 a pure 32bits mul implementation - add a testcase for l.mul* overflow check Addressed MaxBlue's review comments: - enforced instructions can be only accessible in supervisor mode - add exception check in softmmu mode if the CPU is not in supervisor mode v9: Addressed Blue's review comments: - fix jump instructions - fix some instruction decoding Addressed AndreasPaolo's review comments: - rename intrpt*.c to interrupt*.c - use one-space indentation in Copyright Notice - remove unused header in cpu.c - remove/comment unimplement or64 code - remove unused macro - move feature into OpenRISCCPU from CPUOpenRISCState - move tcg_inited into initfn - remove reset in openrisc_*_initfn -combine target-machine into target-stubs v8: Addressed Max's review comments: - fix l.div*. Addressed Blue's review comments: - using qemu_log instead of printf. Addressed Peter's review comments: - fix load_kernel. Addressed PeterAndreas's review comments: - thanks Andreas's r178 example, switch to QOM from CPUArchState. v7: Addressed Max's review comments: - fix l.div*. - add a div testcase. - add return -1 to every failed test. Addressed Peter's review comments: - fix load_kernel(). Addressed WeiRen's review comments: - fix typo, l.div and load_kernel(). v6: Addressed Blue's review comments: - reimplement l.mul* l.mfspr. - fix l.mtspr l.sub. - some English typo fix. - some coding style fix. Addressed Max's review comments: - replace NE2000 with OpenCores 10/100 ethernet adapter, thanks for his patch. v5: Addressed Blue's review comments: - reimplement l.mul* l.mtspr l.add* l.sub* and more. - shoot bugs with --enable-debug-tcg. v4: Addressed Max's review comments: - fix l.div l.mac* l.mul*, and more. Addressed Richard, Wei-Ren and Andreas's review comments: - replace tcg_temp_new_i32 with tcg_temp_local_new_i32 in l.div translation. Addressed Andreas's review comments: - update to suit Makefile system. - add UPR CPUCFGR and MMUCFGR impelement. - add instruction check functions. v3: Addressed Stefan and Andreas's review comments: - use QEMU and OpenRISC's official name. Addressed Andreas's review comments: - reimplement cpu QOM. - combine target stubs and QOM implement. - use new commit message and subject. Addressed Max's review comments: - handle div zero exception. - reimplement float point instructions. - fix l.mac*, l.mul*, and more. v2: Addressed Malc, Weiren, Andreas and Blue's review comments: - reimplement cpu QOM. Addressed Andreas's review comments: - reimplement machine. - rewrite the Copyright Notice using better format. Addressed Blue and Weiren's review comments: - compiling with AREG0 and remove global env, no dyngen-exe longer. Addressed Max, Blue and Weiren's review comments: - handle div zero exception. - handle illegal instruction. Addressed Blue's review comments: - separate do_interrupt into intrpt.c form intrpt_helper.c. - add QEMU_NORETURN to raise_exception. - reimplement float instrutions. - fix type of linux syscall and termbits. - reimplement sim board. - use the LGPL web URL in Copyright Notice. - reimplemt branch instructions. - split taregt stubs, QOM and machine. v1: - add QEMU OpenRISC support. - well tested on x64 machine, and final tested x86 machine. Jia Liu (15): target-or32: Add target stubs and QOM cpu target-or32: Add MMU support target-or32: Add interrupt support target-or32: Add exception support target-or32: Add int instruction helpers target-or32: Add float instruction helpers target-or32: Add instruction translation target-or32: Add PIC support target-or32: Add timer support target-or32: Add a IIS dummy board target-or32: Add system instructions target-or32: Add gdb stub support target-or32: Add linux syscall, signal and termbits target-or32: Add linux user support target-or32: Add testcses arch_init.c |2 + arch_init.h |1
Re: [Qemu-devel] [PATCH v10 00/15] QEMU OpenRISC support
Hi Blue, and other maintainers, On Sat, Jul 28, 2012 at 8:13 PM, Blue Swirl blauwir...@gmail.com wrote: On Fri, Jul 20, 2012 at 7:50 AM, Jia Liu pro...@gmail.com wrote: This is the OpenCores OpenRISC 1200 support for QEMU. Full implementation of the system-model and linux-user-model support. OpenRISC 1200 is a OpenCores open source CPU, its architecture manual can be found at http://opencores.org/svnget,or1k?file=/trunk/docs/openrisc_arch.pdf A OpenRISC Linux kernel contain initramfs for qemu-system-or32 testing can be found at https://docs.google.com/file/d/0BxeTrz3x0CBLSjR3Sk5Vd3h1eDA/edit?pli=1 A OpenRISC hello-world program for qemu-or32 testing can be found at https://docs.google.com/file/d/0BxeTrz3x0CBLN3RSWUFNYktrU2M/edit?pli=1 Signed-off-by: Jia Liu pro...@gmail.com Thanks, applied all. Thank you very much! Thank you all for giving me so much comment what make me know qemu better. --- Version History: v10: Addressed Peter's review comments: - replace field() with extract32() using for decode Addressed Max's review comments: - reimplement l.ff1 and l.fl1 by using ctz32() and clz32() - make helper func mul32 a pure 32bits mul implementation - add a testcase for l.mul* overflow check Addressed MaxBlue's review comments: - enforced instructions can be only accessible in supervisor mode - add exception check in softmmu mode if the CPU is not in supervisor mode v9: Addressed Blue's review comments: - fix jump instructions - fix some instruction decoding Addressed AndreasPaolo's review comments: - rename intrpt*.c to interrupt*.c - use one-space indentation in Copyright Notice - remove unused header in cpu.c - remove/comment unimplement or64 code - remove unused macro - move feature into OpenRISCCPU from CPUOpenRISCState - move tcg_inited into initfn - remove reset in openrisc_*_initfn -combine target-machine into target-stubs v8: Addressed Max's review comments: - fix l.div*. Addressed Blue's review comments: - using qemu_log instead of printf. Addressed Peter's review comments: - fix load_kernel. Addressed PeterAndreas's review comments: - thanks Andreas's r178 example, switch to QOM from CPUArchState. v7: Addressed Max's review comments: - fix l.div*. - add a div testcase. - add return -1 to every failed test. Addressed Peter's review comments: - fix load_kernel(). Addressed WeiRen's review comments: - fix typo, l.div and load_kernel(). v6: Addressed Blue's review comments: - reimplement l.mul* l.mfspr. - fix l.mtspr l.sub. - some English typo fix. - some coding style fix. Addressed Max's review comments: - replace NE2000 with OpenCores 10/100 ethernet adapter, thanks for his patch. v5: Addressed Blue's review comments: - reimplement l.mul* l.mtspr l.add* l.sub* and more. - shoot bugs with --enable-debug-tcg. v4: Addressed Max's review comments: - fix l.div l.mac* l.mul*, and more. Addressed Richard, Wei-Ren and Andreas's review comments: - replace tcg_temp_new_i32 with tcg_temp_local_new_i32 in l.div translation. Addressed Andreas's review comments: - update to suit Makefile system. - add UPR CPUCFGR and MMUCFGR impelement. - add instruction check functions. v3: Addressed Stefan and Andreas's review comments: - use QEMU and OpenRISC's official name. Addressed Andreas's review comments: - reimplement cpu QOM. - combine target stubs and QOM implement. - use new commit message and subject. Addressed Max's review comments: - handle div zero exception. - reimplement float point instructions. - fix l.mac*, l.mul*, and more. v2: Addressed Malc, Weiren, Andreas and Blue's review comments: - reimplement cpu QOM. Addressed Andreas's review comments: - reimplement machine. - rewrite the Copyright Notice using better format. Addressed Blue and Weiren's review comments: - compiling with AREG0 and remove global env, no dyngen-exe longer. Addressed Max, Blue and Weiren's review comments: - handle div zero exception. - handle illegal instruction. Addressed Blue's review comments: - separate do_interrupt into intrpt.c form intrpt_helper.c. - add QEMU_NORETURN to raise_exception. - reimplement float instrutions. - fix type of linux syscall and termbits. - reimplement sim board. - use the LGPL web URL in Copyright Notice. - reimplemt branch instructions. - split taregt stubs, QOM and machine. v1: - add QEMU OpenRISC support. - well tested on x64 machine, and final tested x86 machine. Jia Liu (15): target-or32: Add target stubs and QOM cpu target-or32: Add MMU support target-or32: Add interrupt support target-or32: Add exception support target-or32: Add int instruction helpers target-or32: Add float instruction helpers target-or32: Add instruction translation target-or32: Add PIC support target-or32: Add timer support target-or32: Add a IIS dummy board target-or32: Add system instructions target-or32: Add gdb stub support
Re: [Qemu-devel] [PATCH v10 00/15] QEMU OpenRISC support
ping On Fri, Jul 20, 2012 at 3:50 PM, Jia Liu pro...@gmail.com wrote: This is the OpenCores OpenRISC 1200 support for QEMU. Full implementation of the system-model and linux-user-model support. OpenRISC 1200 is a OpenCores open source CPU, its architecture manual can be found at http://opencores.org/svnget,or1k?file=/trunk/docs/openrisc_arch.pdf A OpenRISC Linux kernel contain initramfs for qemu-system-or32 testing can be found at https://docs.google.com/file/d/0BxeTrz3x0CBLSjR3Sk5Vd3h1eDA/edit?pli=1 A OpenRISC hello-world program for qemu-or32 testing can be found at https://docs.google.com/file/d/0BxeTrz3x0CBLN3RSWUFNYktrU2M/edit?pli=1 Signed-off-by: Jia Liu pro...@gmail.com --- Version History: v10: Addressed Peter's review comments: - replace field() with extract32() using for decode Addressed Max's review comments: - reimplement l.ff1 and l.fl1 by using ctz32() and clz32() - make helper func mul32 a pure 32bits mul implementation - add a testcase for l.mul* overflow check Addressed MaxBlue's review comments: - enforced instructions can be only accessible in supervisor mode - add exception check in softmmu mode if the CPU is not in supervisor mode v9: Addressed Blue's review comments: - fix jump instructions - fix some instruction decoding Addressed AndreasPaolo's review comments: - rename intrpt*.c to interrupt*.c - use one-space indentation in Copyright Notice - remove unused header in cpu.c - remove/comment unimplement or64 code - remove unused macro - move feature into OpenRISCCPU from CPUOpenRISCState - move tcg_inited into initfn - remove reset in openrisc_*_initfn -combine target-machine into target-stubs v8: Addressed Max's review comments: - fix l.div*. Addressed Blue's review comments: - using qemu_log instead of printf. Addressed Peter's review comments: - fix load_kernel. Addressed PeterAndreas's review comments: - thanks Andreas's r178 example, switch to QOM from CPUArchState. v7: Addressed Max's review comments: - fix l.div*. - add a div testcase. - add return -1 to every failed test. Addressed Peter's review comments: - fix load_kernel(). Addressed WeiRen's review comments: - fix typo, l.div and load_kernel(). v6: Addressed Blue's review comments: - reimplement l.mul* l.mfspr. - fix l.mtspr l.sub. - some English typo fix. - some coding style fix. Addressed Max's review comments: - replace NE2000 with OpenCores 10/100 ethernet adapter, thanks for his patch. v5: Addressed Blue's review comments: - reimplement l.mul* l.mtspr l.add* l.sub* and more. - shoot bugs with --enable-debug-tcg. v4: Addressed Max's review comments: - fix l.div l.mac* l.mul*, and more. Addressed Richard, Wei-Ren and Andreas's review comments: - replace tcg_temp_new_i32 with tcg_temp_local_new_i32 in l.div translation. Addressed Andreas's review comments: - update to suit Makefile system. - add UPR CPUCFGR and MMUCFGR impelement. - add instruction check functions. v3: Addressed Stefan and Andreas's review comments: - use QEMU and OpenRISC's official name. Addressed Andreas's review comments: - reimplement cpu QOM. - combine target stubs and QOM implement. - use new commit message and subject. Addressed Max's review comments: - handle div zero exception. - reimplement float point instructions. - fix l.mac*, l.mul*, and more. v2: Addressed Malc, Weiren, Andreas and Blue's review comments: - reimplement cpu QOM. Addressed Andreas's review comments: - reimplement machine. - rewrite the Copyright Notice using better format. Addressed Blue and Weiren's review comments: - compiling with AREG0 and remove global env, no dyngen-exe longer. Addressed Max, Blue and Weiren's review comments: - handle div zero exception. - handle illegal instruction. Addressed Blue's review comments: - separate do_interrupt into intrpt.c form intrpt_helper.c. - add QEMU_NORETURN to raise_exception. - reimplement float instrutions. - fix type of linux syscall and termbits. - reimplement sim board. - use the LGPL web URL in Copyright Notice. - reimplemt branch instructions. - split taregt stubs, QOM and machine. v1: - add QEMU OpenRISC support. - well tested on x64 machine, and final tested x86 machine. Jia Liu (15): target-or32: Add target stubs and QOM cpu target-or32: Add MMU support target-or32: Add interrupt support target-or32: Add exception support target-or32: Add int instruction helpers target-or32: Add float instruction helpers target-or32: Add instruction translation target-or32: Add PIC support target-or32: Add timer support target-or32: Add a IIS dummy board target-or32: Add system instructions target-or32: Add gdb stub support target-or32: Add linux syscall, signal and termbits target-or32: Add linux user support target-or32: Add testcses arch_init.c |2 + arch_init.h |1 + configure
[Qemu-devel] [PATCH v10 00/15] QEMU OpenRISC support
This is the OpenCores OpenRISC 1200 support for QEMU. Full implementation of the system-model and linux-user-model support. OpenRISC 1200 is a OpenCores open source CPU, its architecture manual can be found at http://opencores.org/svnget,or1k?file=/trunk/docs/openrisc_arch.pdf A OpenRISC Linux kernel contain initramfs for qemu-system-or32 testing can be found at https://docs.google.com/file/d/0BxeTrz3x0CBLSjR3Sk5Vd3h1eDA/edit?pli=1 A OpenRISC hello-world program for qemu-or32 testing can be found at https://docs.google.com/file/d/0BxeTrz3x0CBLN3RSWUFNYktrU2M/edit?pli=1 Signed-off-by: Jia Liu pro...@gmail.com --- Version History: v10: Addressed Peter's review comments: - replace field() with extract32() using for decode Addressed Max's review comments: - reimplement l.ff1 and l.fl1 by using ctz32() and clz32() - make helper func mul32 a pure 32bits mul implementation - add a testcase for l.mul* overflow check Addressed MaxBlue's review comments: - enforced instructions can be only accessible in supervisor mode - add exception check in softmmu mode if the CPU is not in supervisor mode v9: Addressed Blue's review comments: - fix jump instructions - fix some instruction decoding Addressed AndreasPaolo's review comments: - rename intrpt*.c to interrupt*.c - use one-space indentation in Copyright Notice - remove unused header in cpu.c - remove/comment unimplement or64 code - remove unused macro - move feature into OpenRISCCPU from CPUOpenRISCState - move tcg_inited into initfn - remove reset in openrisc_*_initfn -combine target-machine into target-stubs v8: Addressed Max's review comments: - fix l.div*. Addressed Blue's review comments: - using qemu_log instead of printf. Addressed Peter's review comments: - fix load_kernel. Addressed PeterAndreas's review comments: - thanks Andreas's r178 example, switch to QOM from CPUArchState. v7: Addressed Max's review comments: - fix l.div*. - add a div testcase. - add return -1 to every failed test. Addressed Peter's review comments: - fix load_kernel(). Addressed WeiRen's review comments: - fix typo, l.div and load_kernel(). v6: Addressed Blue's review comments: - reimplement l.mul* l.mfspr. - fix l.mtspr l.sub. - some English typo fix. - some coding style fix. Addressed Max's review comments: - replace NE2000 with OpenCores 10/100 ethernet adapter, thanks for his patch. v5: Addressed Blue's review comments: - reimplement l.mul* l.mtspr l.add* l.sub* and more. - shoot bugs with --enable-debug-tcg. v4: Addressed Max's review comments: - fix l.div l.mac* l.mul*, and more. Addressed Richard, Wei-Ren and Andreas's review comments: - replace tcg_temp_new_i32 with tcg_temp_local_new_i32 in l.div translation. Addressed Andreas's review comments: - update to suit Makefile system. - add UPR CPUCFGR and MMUCFGR impelement. - add instruction check functions. v3: Addressed Stefan and Andreas's review comments: - use QEMU and OpenRISC's official name. Addressed Andreas's review comments: - reimplement cpu QOM. - combine target stubs and QOM implement. - use new commit message and subject. Addressed Max's review comments: - handle div zero exception. - reimplement float point instructions. - fix l.mac*, l.mul*, and more. v2: Addressed Malc, Weiren, Andreas and Blue's review comments: - reimplement cpu QOM. Addressed Andreas's review comments: - reimplement machine. - rewrite the Copyright Notice using better format. Addressed Blue and Weiren's review comments: - compiling with AREG0 and remove global env, no dyngen-exe longer. Addressed Max, Blue and Weiren's review comments: - handle div zero exception. - handle illegal instruction. Addressed Blue's review comments: - separate do_interrupt into intrpt.c form intrpt_helper.c. - add QEMU_NORETURN to raise_exception. - reimplement float instrutions. - fix type of linux syscall and termbits. - reimplement sim board. - use the LGPL web URL in Copyright Notice. - reimplemt branch instructions. - split taregt stubs, QOM and machine. v1: - add QEMU OpenRISC support. - well tested on x64 machine, and final tested x86 machine. Jia Liu (15): target-or32: Add target stubs and QOM cpu target-or32: Add MMU support target-or32: Add interrupt support target-or32: Add exception support target-or32: Add int instruction helpers target-or32: Add float instruction helpers target-or32: Add instruction translation target-or32: Add PIC support target-or32: Add timer support target-or32: Add a IIS dummy board target-or32: Add system instructions target-or32: Add gdb stub support target-or32: Add linux syscall, signal and termbits target-or32: Add linux user support target-or32: Add testcses arch_init.c |2 + arch_init.h |1 + configure | 15 +- cpu-exec.c | 19 + default-configs/or32-linux-user.mak |1 + default-configs/or32-softmmu.mak|4 + elf.h
