Re: [Qemu-devel] [PATCH v10.5 00/20] tcg: generic vector operations

2018-01-25 Thread Peter Maydell 
On 17 January 2018 at 16:14, Richard Henderson
 wrote:
> Richard Henderson (21):
>   tcg: Allow multiple word entries into the constant pool
>   tcg: Add types and basic operations for host vectors
>   tcg: Standardize integral arguments to expanders
>   tcg: Add generic vector expanders
>   tcg: Loosen vec_gen_op* typecheck rules
>   tcg: Add generic vector ops for constant shifts
>   tcg: Add generic vector ops for comparisons
>   tcg: Add generic vector ops for multiplication
>   tcg: Add generic helpers for saturating arithmetic
>   tcg: Add generic vector helpers with a scalar operand
>   tcg/optimize: Handle vector opcodes during optimize
>   target/arm: Align vector registers
>   target/arm: Use vector infrastructure for aa64 add/sub/logic
>   target/arm: Use vector infrastructure for aa64 mov/not/neg
>   target/arm: Use vector infrastructure for aa64 dup/movi
>   target/arm: Use vector infrastructure for aa64 constant shifts
>   target/arm: Use vector infrastructure for aa64 compares
>   target/arm: Use vector infrastructure for aa64 multiplies
>   target/arm: Use vector infrastructure for aa64 orr/bic immediate
>   tcg/i386: Add vector operations
>   tcg/aarch64: Add vector operations

I've reviewed the arm frontend patches, at least. The tcg backend
stuff is a combination of huge patches and not an area of the
code I'm familiar with, so I've left those in the hope that
somebody else will look at them...

thanks
-- PMM

Re: [Qemu-devel] [PATCH v10.5 00/20] tcg: generic vector operations

2018-01-17 Thread no-reply 
Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20180117161435.28981-1-richard.hender...@linaro.org
Subject: [Qemu-devel] [PATCH v10.5 00/20] tcg: generic vector operations

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 t [tag update]
patchew/1516203816-19374-1-git-send-email-imamm...@redhat.com -> 
patchew/1516203816-19374-1-git-send-email-imamm...@redhat.com
 * [new tag]   
patchew/20180117161435.28981-1-richard.hender...@linaro.org -> 
patchew/20180117161435.28981-1-richard.hender...@linaro.org
 t [tag update]patchew/cover.1513342045.git.be...@igalia.com -> 
patchew/cover.1513342045.git.be...@igalia.com
Switched to a new branch 'test'
4a44f8555f tcg/aarch64: Add vector operations
3f13bbe828 tcg/i386: Add vector operations
728e947a0a target/arm: Use vector infrastructure for aa64 orr/bic immediate
34b5e36472 target/arm: Use vector infrastructure for aa64 multiplies
18e6130136 target/arm: Use vector infrastructure for aa64 compares
c81ef1ce77 target/arm: Use vector infrastructure for aa64 constant shifts
9cc821fe02 target/arm: Use vector infrastructure for aa64 dup/movi
3b2c705f87 target/arm: Use vector infrastructure for aa64 mov/not/neg
87e3acd50c target/arm: Use vector infrastructure for aa64 add/sub/logic
11664047d7 target/arm: Align vector registers
cb396195d6 tcg/optimize: Handle vector opcodes during optimize
6c3ebb28e1 tcg: Add generic vector helpers with a scalar operand
36b51bc4e7 tcg: Add generic helpers for saturating arithmetic
1e1d25fd62 tcg: Add generic vector ops for multiplication
bc56f0c86e tcg: Add generic vector ops for comparisons
7cb9933b88 tcg: Add generic vector ops for constant shifts
b71baaf8c2 tcg: Add generic vector expanders
8c13a53e09 tcg: Standardize integral arguments to expanders
2fb37be608 tcg: Add types and basic operations for host vectors
d5cc9c8771 tcg: Allow multiple word entries into the constant pool

=== OUTPUT BEGIN ===
Checking PATCH 1/20: tcg: Allow multiple word entries into the constant pool...
ERROR: spaces prohibited around that ':' (ctx:WxW)
#23: FILE: tcg/tcg-pool.inc.c:26:
+int addend  : 32;
 ^

ERROR: spaces prohibited around that ':' (ctx:WxW)
#24: FILE: tcg/tcg-pool.inc.c:27:
+int rtype   : 16;
 ^

ERROR: spaces prohibited around that ':' (ctx:WxW)
#25: FILE: tcg/tcg-pool.inc.c:28:
+int nlong   : 16;
 ^

total: 3 errors, 0 warnings, 156 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 2/20: tcg: Add types and basic operations for host vectors...
ERROR: externs should be avoided in .c files
#137: FILE: tcg/tcg-op-vec.c:37:
+extern TCGv_i32 TCGV_LOW_link_error(TCGv_i64);

ERROR: externs should be avoided in .c files
#138: FILE: tcg/tcg-op-vec.c:38:
+extern TCGv_i32 TCGV_HIGH_link_error(TCGv_i64);

ERROR: Macros with complex values should be enclosed in parenthesis
#535: FILE: tcg/tcg-opc.h:209:
+#define IMPLVEC  TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec)

WARNING: line over 80 characters
#538: FILE: tcg/tcg-opc.h:212:
+DEF(movi_vec, 1, 0, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) /* vecl defines 
const args */

ERROR: Macros with complex values should be enclosed in parenthesis
#800: FILE: tcg/tcg.h:621:
+#define TCGOP_VECL(X) (X)->param1

ERROR: Macros with complex values should be enclosed in parenthesis
#801: FILE: tcg/tcg.h:622:
+#define TCGOP_VECE(X) (X)->param2

total: 5 errors, 1 warnings, 807 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 3/20: tcg: Standardize integral arguments to expanders...
Checking PATCH 4/20: tcg: Add generic vector expanders...
ERROR: spaces required around that '&' (ctx:WxO)
#350: FILE: accel/tcg/tcg-runtime-gvec.c:311:
+*(vec64 *)(d + i) = *(vec64 *)(a + i) &~ *(vec64 *)(b + i);
   ^

ERROR: space prohibited after that '~' (ctx:OxW)
#350: FILE: accel/tcg/tcg-runtime-gvec.c:311:
+*(vec64 *)(d + i) = *(vec64 *)(a + i) &~ *(vec64 *)(b + i);
^

ERROR: spaces required around that '|' (ct

[Qemu-devel] [PATCH v10.5 00/20] tcg: generic vector operations

2018-01-17 Thread Richard Henderson 
Changes since v10:
  * Squashed a fixup patch which escaped my attention while preparing
the patch set.  Ho hum.

Changes since v9:
  * Detect whether __attribute__((vector_size(16))) operations are
supported by the host compiler.  This includes the case affecting
ppc64 where gcc-4.8.5 crashes.  Note that gcc-7.2 does pass the
test on ppc64.

  * Dropped support for vector interleaves and element size changes.
My target/arm patches were failing RISU checks on a big-endian host.
I need to re-think what to do about host endianness and target
representation of vector operations crossing lanes.  For now, only
support generic vector operations that are agnostic to element order.


r~


Richard Henderson (21):
  tcg: Allow multiple word entries into the constant pool
  tcg: Add types and basic operations for host vectors
  tcg: Standardize integral arguments to expanders
  tcg: Add generic vector expanders
  tcg: Loosen vec_gen_op* typecheck rules
  tcg: Add generic vector ops for constant shifts
  tcg: Add generic vector ops for comparisons
  tcg: Add generic vector ops for multiplication
  tcg: Add generic helpers for saturating arithmetic
  tcg: Add generic vector helpers with a scalar operand
  tcg/optimize: Handle vector opcodes during optimize
  target/arm: Align vector registers
  target/arm: Use vector infrastructure for aa64 add/sub/logic
  target/arm: Use vector infrastructure for aa64 mov/not/neg
  target/arm: Use vector infrastructure for aa64 dup/movi
  target/arm: Use vector infrastructure for aa64 constant shifts
  target/arm: Use vector infrastructure for aa64 compares
  target/arm: Use vector infrastructure for aa64 multiplies
  target/arm: Use vector infrastructure for aa64 orr/bic immediate
  tcg/i386: Add vector operations
  tcg/aarch64: Add vector operations

 Makefile.target  |4 +-
 accel/tcg/tcg-runtime.h  |  118 +++
 target/arm/cpu.h |2 +-
 tcg/aarch64/tcg-target.h |   25 +-
 tcg/aarch64/tcg-target.opc.h |3 +
 tcg/i386/tcg-target.h|   41 +-
 tcg/i386/tcg-target.opc.h|   13 +
 tcg/tcg-gvec-desc.h  |   49 +
 tcg/tcg-op-gvec.h|  297 ++
 tcg/tcg-op.h |   55 +-
 tcg/tcg-opc.h|   47 +
 tcg/tcg.h|   78 ++
 accel/tcg/tcg-runtime-gvec.c |  997 +++
 target/arm/translate-a64.c   |  974 +-
 tcg/aarch64/tcg-target.inc.c |  607 +++-
 tcg/i386/tcg-target.inc.c| 1043 +++-
 tcg/optimize.c   |  150 +--
 tcg/tcg-op-gvec.c| 2226 ++
 tcg/tcg-op-vec.c |  474 +
 tcg/tcg-op.c |   42 +-
 tcg/tcg-pool.inc.c   |  115 ++-
 tcg/tcg.c|  129 ++-
 accel/tcg/Makefile.objs  |2 +-
 configure|   48 +
 tcg/README   |   95 ++
 25 files changed, 7151 insertions(+), 483 deletions(-)
 create mode 100644 tcg/aarch64/tcg-target.opc.h
 create mode 100644 tcg/i386/tcg-target.opc.h
 create mode 100644 tcg/tcg-gvec-desc.h
 create mode 100644 tcg/tcg-op-gvec.h
 create mode 100644 accel/tcg/tcg-runtime-gvec.c
 create mode 100644 tcg/tcg-op-gvec.c
 create mode 100644 tcg/tcg-op-vec.c

-- 
2.14.3


Richard Henderson (20):
  tcg: Allow multiple word entries into the constant pool
  tcg: Add types and basic operations for host vectors
  tcg: Standardize integral arguments to expanders
  tcg: Add generic vector expanders
  tcg: Add generic vector ops for constant shifts
  tcg: Add generic vector ops for comparisons
  tcg: Add generic vector ops for multiplication
  tcg: Add generic helpers for saturating arithmetic
  tcg: Add generic vector helpers with a scalar operand
  tcg/optimize: Handle vector opcodes during optimize
  target/arm: Align vector registers
  target/arm: Use vector infrastructure for aa64 add/sub/logic
  target/arm: Use vector infrastructure for aa64 mov/not/neg
  target/arm: Use vector infrastructure for aa64 dup/movi
  target/arm: Use vector infrastructure for aa64 constant shifts
  target/arm: Use vector infrastructure for aa64 compares
  target/arm: Use vector infrastructure for aa64 multiplies
  target/arm: Use vector infrastructure for aa64 orr/bic immediate
  tcg/i386: Add vector operations
  tcg/aarch64: Add vector operations

 Makefile.target  |4 +-
 accel/tcg/tcg-runtime.h  |  118 +++
 target/arm/cpu.h |2 +-
 tcg/aarch64/tcg-target.h |   25 +-
 tcg/aarch64/tcg-target.opc.h |3 +
 tcg/i386/tcg-target.h|   41 +-
 tcg/i386/tcg-target.opc.h|   13 +
 tcg/tcg-gvec-desc.h  |   49 +
 tcg/tcg-op-gvec.h|  297 ++
 tcg/tcg-op.h |   55 +-
 tcg/tcg-opc.h|   47 +
 tcg/tcg.h|   78 ++
 accel/tcg/tcg-runtime-gvec.c |  997 +++
 target/arm/translate-a64.c   |  974 +-