subject:"\[Qemu\-devel\] \[PATCH v12 01\/27\] Pass generic CPUState to gen_intermediate

Re: [Qemu-devel] [PATCH v12 01/27] Pass generic CPUState to gen_intermediate_code()

2017-07-11 Thread Alex Bennée


Lluís Vilanova  writes:

> Needed to implement a target-agnostic gen_intermediate_code() in the
> future.
>
> Signed-off-by: Lluís Vilanova 
> Reviewed-by: David Gibson 
> Reviewed-by: Richard Henderson 

Reviewed-by: Alex Bennée 

> ---
>  accel/tcg/translate-all.c |2 +-
>  include/exec/exec-all.h   |2 +-
>  target/alpha/translate.c  |5 ++---
>  target/arm/translate-a64.c|6 +++---
>  target/arm/translate.c|6 +++---
>  target/arm/translate.h|4 ++--
>  target/cris/translate.c   |7 +++
>  target/hppa/translate.c   |5 ++---
>  target/i386/translate.c   |5 ++---
>  target/lm32/translate.c   |4 ++--
>  target/m68k/translate.c   |5 ++---
>  target/microblaze/translate.c |4 ++--
>  target/mips/translate.c   |5 ++---
>  target/moxie/translate.c  |4 ++--
>  target/nios2/translate.c  |5 ++---
>  target/openrisc/translate.c   |4 ++--
>  target/ppc/translate.c|5 ++---
>  target/s390x/translate.c  |5 ++---
>  target/sh4/translate.c|5 ++---
>  target/sparc/translate.c  |5 ++---
>  target/tilegx/translate.c |5 ++---
>  target/tricore/translate.c|5 ++---
>  target/unicore32/translate.c  |5 ++---
>  target/xtensa/translate.c |5 ++---
>  24 files changed, 49 insertions(+), 64 deletions(-)
>
> diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
> index f6ad46b613..2dc93f420a 100644
> --- a/accel/tcg/translate-all.c
> +++ b/accel/tcg/translate-all.c
> @@ -1299,7 +1299,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
>  tcg_func_start(_ctx);
>
>  tcg_ctx.cpu = ENV_GET_CPU(env);
> -gen_intermediate_code(env, tb);
> +gen_intermediate_code(cpu, tb);
>  tcg_ctx.cpu = NULL;
>
>  trace_translate_block(tb, tb->pc, tb->tc_ptr);
> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
> index 724ec73dce..0826894ec5 100644
> --- a/include/exec/exec-all.h
> +++ b/include/exec/exec-all.h
> @@ -43,7 +43,7 @@ typedef ram_addr_t tb_page_addr_t;
>
>  #include "qemu/log.h"
>
> -void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
> +void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb);
>  void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
>target_ulong *data);
>
> diff --git a/target/alpha/translate.c b/target/alpha/translate.c
> index 232af9e177..7b39101053 100644
> --- a/target/alpha/translate.c
> +++ b/target/alpha/translate.c
> @@ -2911,10 +2911,9 @@ static ExitStatus translate_one(DisasContext *ctx, 
> uint32_t insn)
>  return ret;
>  }
>
> -void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb)
> +void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
>  {
> -AlphaCPU *cpu = alpha_env_get_cpu(env);
> -CPUState *cs = CPU(cpu);
> +CPUAlphaState *env = cs->env_ptr;
>  DisasContext ctx, *ctxp = 
>  target_ulong pc_start;
>  target_ulong pc_mask;
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index e55547d95d..f9bd1a9679 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -11190,10 +11190,10 @@ static void disas_a64_insn(CPUARMState *env, 
> DisasContext *s)
>  free_tmp_a64(s);
>  }
>
> -void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
> +void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb)
>  {
> -CPUState *cs = CPU(cpu);
> -CPUARMState *env = >env;
> +CPUARMState *env = cs->env_ptr;
> +ARMCPU *cpu = arm_env_get_cpu(env);
>  DisasContext dc1, *dc = 
>  target_ulong pc_start;
>  target_ulong next_page_start;
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 0862f9e4aa..e80cc357c1 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -11787,10 +11787,10 @@ static bool insn_crosses_page(CPUARMState *env, 
> DisasContext *s)
>  }
>
>  /* generate intermediate code for basic block 'tb'.  */
> -void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
> +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
>  {
> +CPUARMState *env = cs->env_ptr;
>  ARMCPU *cpu = arm_env_get_cpu(env);
> -CPUState *cs = CPU(cpu);
>  DisasContext dc1, *dc = 
>  target_ulong pc_start;
>  target_ulong next_page_start;
> @@ -11804,7 +11804,7 @@ void gen_intermediate_code(CPUARMState *env, 
> TranslationBlock *tb)
>   * the A32/T32 complexity to do with conditional execution/IT blocks/etc.
>   */
>  if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
> -gen_intermediate_code_a64(cpu, tb);
> +gen_intermediate_code_a64(cs, tb);
>  return;
>  }
>
> diff --git a/target/arm/translate.h b/target/arm/translate.h
> index

[Qemu-devel] [PATCH v12 01/27] Pass generic CPUState to gen_intermediate_code()

2017-07-07 Thread Lluís Vilanova

Needed to implement a target-agnostic gen_intermediate_code() in the
future.

Signed-off-by: Lluís Vilanova 
Reviewed-by: David Gibson 
Reviewed-by: Richard Henderson 
---
 accel/tcg/translate-all.c |2 +-
 include/exec/exec-all.h   |2 +-
 target/alpha/translate.c  |5 ++---
 target/arm/translate-a64.c|6 +++---
 target/arm/translate.c|6 +++---
 target/arm/translate.h|4 ++--
 target/cris/translate.c   |7 +++
 target/hppa/translate.c   |5 ++---
 target/i386/translate.c   |5 ++---
 target/lm32/translate.c   |4 ++--
 target/m68k/translate.c   |5 ++---
 target/microblaze/translate.c |4 ++--
 target/mips/translate.c   |5 ++---
 target/moxie/translate.c  |4 ++--
 target/nios2/translate.c  |5 ++---
 target/openrisc/translate.c   |4 ++--
 target/ppc/translate.c|5 ++---
 target/s390x/translate.c  |5 ++---
 target/sh4/translate.c|5 ++---
 target/sparc/translate.c  |5 ++---
 target/tilegx/translate.c |5 ++---
 target/tricore/translate.c|5 ++---
 target/unicore32/translate.c  |5 ++---
 target/xtensa/translate.c |5 ++---
 24 files changed, 49 insertions(+), 64 deletions(-)

diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index f6ad46b613..2dc93f420a 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -1299,7 +1299,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
 tcg_func_start(_ctx);
 
 tcg_ctx.cpu = ENV_GET_CPU(env);
-gen_intermediate_code(env, tb);
+gen_intermediate_code(cpu, tb);
 tcg_ctx.cpu = NULL;
 
 trace_translate_block(tb, tb->pc, tb->tc_ptr);
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 724ec73dce..0826894ec5 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -43,7 +43,7 @@ typedef ram_addr_t tb_page_addr_t;
 
 #include "qemu/log.h"
 
-void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
+void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb);
 void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
   target_ulong *data);
 
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 232af9e177..7b39101053 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -2911,10 +2911,9 @@ static ExitStatus translate_one(DisasContext *ctx, 
uint32_t insn)
 return ret;
 }
 
-void gen_intermediate_code(CPUAlphaState *env, struct TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
 {
-AlphaCPU *cpu = alpha_env_get_cpu(env);
-CPUState *cs = CPU(cpu);
+CPUAlphaState *env = cs->env_ptr;
 DisasContext ctx, *ctxp = 
 target_ulong pc_start;
 target_ulong pc_mask;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index e55547d95d..f9bd1a9679 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -11190,10 +11190,10 @@ static void disas_a64_insn(CPUARMState *env, 
DisasContext *s)
 free_tmp_a64(s);
 }
 
-void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb)
+void gen_intermediate_code_a64(CPUState *cs, TranslationBlock *tb)
 {
-CPUState *cs = CPU(cpu);
-CPUARMState *env = >env;
+CPUARMState *env = cs->env_ptr;
+ARMCPU *cpu = arm_env_get_cpu(env);
 DisasContext dc1, *dc = 
 target_ulong pc_start;
 target_ulong next_page_start;
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 0862f9e4aa..e80cc357c1 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -11787,10 +11787,10 @@ static bool insn_crosses_page(CPUARMState *env, 
DisasContext *s)
 }
 
 /* generate intermediate code for basic block 'tb'.  */
-void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
 {
+CPUARMState *env = cs->env_ptr;
 ARMCPU *cpu = arm_env_get_cpu(env);
-CPUState *cs = CPU(cpu);
 DisasContext dc1, *dc = 
 target_ulong pc_start;
 target_ulong next_page_start;
@@ -11804,7 +11804,7 @@ void gen_intermediate_code(CPUARMState *env, 
TranslationBlock *tb)
  * the A32/T32 complexity to do with conditional execution/IT blocks/etc.
  */
 if (ARM_TBFLAG_AARCH64_STATE(tb->flags)) {
-gen_intermediate_code_a64(cpu, tb);
+gen_intermediate_code_a64(cs, tb);
 return;
 }
 
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 15d383d9af..e5da614db5 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -146,7 +146,7 @@ static void disas_set_insn_syndrome(DisasContext *s, 
uint32_t syn)
 
 #ifdef TARGET_AARCH64
 void a64_translate_init(void);
-void gen_intermediate_code_a64(ARMCPU *cpu, TranslationBlock *tb);
+void gen_intermediate_code_a64(CPUState *cpu,

Re: [Qemu-devel] [PATCH v12 01/27] Pass generic CPUState to gen_intermediate_code()

[Qemu-devel] [PATCH v12 01/27] Pass generic CPUState to gen_intermediate_code()

2 matches

Site Navigation

Mail list logo

Footer information