Re: [Qemu-devel] [PATCH v2 00/32] Add ARMv8.2 half-precision functions
Hi, This series failed docker-quick@centos6 build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. Type: series Message-id: 20180208173157.24705-1-alex.ben...@linaro.org Subject: [Qemu-devel] [PATCH v2 00/32] Add ARMv8.2 half-precision functions === TEST SCRIPT BEGIN === #!/bin/bash set -e git submodule update --init dtc # Let docker tests dump environment info export SHOW_ENV=1 export J=8 time make docker-test-quick@centos6 === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 From https://github.com/patchew-project/qemu t [tag update]patchew/20180208172202.9984-1-f4...@amsat.org -> patchew/20180208172202.9984-1-f4...@amsat.org * [new tag] patchew/20180208180019.13683-1-antonios.mota...@huawei.com -> patchew/20180208180019.13683-1-antonios.mota...@huawei.com Switched to a new branch 'test' 828fdf8039 arm/translate-a64: add all single op FP16 to handle_fp_1src_half bb12347df0 arm/translate-a64: implement simd_scalar_three_reg_same_fp16 9d90e658c5 arm/translate-a64: add all FP16 ops in simd_scalar_pairwise 18e4d6f1d2 arm/translate-a64: add FP16 FMOV to simd_mod_imm 487d21785a arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16 e687eee03d arm/helper.c: re-factor rsqrte and add rsqrte_f16 4078596895 arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16 14e2473a01 arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16 0080b9feb1 arm/translate-a64: add FP16 FRECPE 322031a5c9 arm/helper.c: re-factor recpe and add recepe_f16 99396effce arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16 fc0f9dbd0a arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16 ed77588f3f arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16 28b6a6a772 arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16 c8ce2f736d arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16 900561ae36 arm/translate-a64: initial decode for simd_two_reg_misc_fp16 d55f8fd2d4 arm/translate-a64: add FP16 x2 ops for simd_indexed 79200bf33e arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed eebcc3aeb6 arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16 a7d42c109d arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16 f4f8f0083b arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16 f9994103ca arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16 740b571cc7 arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16 221024b870 arm/translate-a64: initial decode for simd_three_reg_same_fp16 e55cd68b2e arm/translate-a64: handle_3same_64 comment fix e961c2bee4 arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV) c177c95091 target/arm/helper: pass explicit fpst to set_rmode 71fe7953f2 target/arm/cpu.h: add additional float_status flags c2bbffe04d target/arm/cpu.h: update comment for half-precision values f5f0e3fa79 target/arm/cpu64: allow fp16 to be disabled ab954b06bc target/arm/cpu64: introduce ARM_V8_FP16 feature bit 7c3b41efe8 include/exec/helper-head.h: support f16 in helper calls === OUTPUT BEGIN === Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc' Cloning into '/var/tmp/patchew-tester-tmp-t07l1ntg/src/dtc'... Submodule path 'dtc': checked out 'e54388015af1fb4bf04d0bca99caba1074d9cc42' BUILD centos6 GEN /var/tmp/patchew-tester-tmp-t07l1ntg/src/docker-src.2018-02-08-14.09.58.21841/qemu.tar Cloning into '/var/tmp/patchew-tester-tmp-t07l1ntg/src/docker-src.2018-02-08-14.09.58.21841/qemu.tar.vroot'... done. Your branch is up-to-date with 'origin/test'. Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc' Cloning into '/var/tmp/patchew-tester-tmp-t07l1ntg/src/docker-src.2018-02-08-14.09.58.21841/qemu.tar.vroot/dtc'... Submodule path 'dtc': checked out 'e54388015af1fb4bf04d0bca99caba1074d9cc42' Submodule 'ui/keycodemapdb' (git://git.qemu.org/keycodemapdb.git) registered for path 'ui/keycodemapdb' Cloning into '/var/tmp/patchew-tester-tmp-t07l1ntg/src/docker-src.2018-02-08-14.09.58.21841/qemu.tar.vroot/ui/keycodemapdb'... Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce' COPYRUNNER RUN test-quick in qemu:centos6 Packages installed: SDL-devel-1.2.14-7.el6_7.1.x86_64 bison-2.4.1-5.el6.x86_64 bzip2-devel-1.0.5-7.el6_0.x86_64 ccache-3.1.6-2.el6.x86_64 csnappy-devel-0-6.20150729gitd7bc683.el6.x86_64 flex-2.5.35-9.el6.x86_64 gcc-4.4.7-18.el6.x86_64 gettext-0.17-18.el6.x86_64 git-1.7.1-9.el6_9.x86_64 glib2-devel-2.28.8-9.el6.x86_64 libepoxy-devel-1.2-3.el6.x86_64 libfdt-devel-1.4.0-1.el6.x86_64 librdmacm-devel-1.0.21-0.el6.x86_64 lzo-devel-2.03-3.1.el6_5.1.x86_64 make-3.81-23.el6.x86_64 mesa-libEGL-devel-11.0.7-4.el6.x86_64 mesa-libgbm-devel-11.0.7-4.el6.x86_64 package g++ is not installed pixman-devel-0.32.8-1.el6.x86_64 spice-glib-devel-0.26-8.el6.x86_64
Re: [Qemu-devel] [PATCH v2 00/32] Add ARMv8.2 half-precision functions
Hi, This series failed docker-build@min-glib build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. Type: series Message-id: 20180208173157.24705-1-alex.ben...@linaro.org Subject: [Qemu-devel] [PATCH v2 00/32] Add ARMv8.2 half-precision functions === TEST SCRIPT BEGIN === #!/bin/bash set -e git submodule update --init dtc # Let docker tests dump environment info export SHOW_ENV=1 export J=8 time make docker-test-build@min-glib === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 Switched to a new branch 'test' 828fdf8039 arm/translate-a64: add all single op FP16 to handle_fp_1src_half bb12347df0 arm/translate-a64: implement simd_scalar_three_reg_same_fp16 9d90e658c5 arm/translate-a64: add all FP16 ops in simd_scalar_pairwise 18e4d6f1d2 arm/translate-a64: add FP16 FMOV to simd_mod_imm 487d21785a arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16 e687eee03d arm/helper.c: re-factor rsqrte and add rsqrte_f16 4078596895 arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16 14e2473a01 arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16 0080b9feb1 arm/translate-a64: add FP16 FRECPE 322031a5c9 arm/helper.c: re-factor recpe and add recepe_f16 99396effce arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16 fc0f9dbd0a arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16 ed77588f3f arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16 28b6a6a772 arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16 c8ce2f736d arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16 900561ae36 arm/translate-a64: initial decode for simd_two_reg_misc_fp16 d55f8fd2d4 arm/translate-a64: add FP16 x2 ops for simd_indexed 79200bf33e arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed eebcc3aeb6 arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16 a7d42c109d arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16 f4f8f0083b arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16 f9994103ca arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16 740b571cc7 arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16 221024b870 arm/translate-a64: initial decode for simd_three_reg_same_fp16 e55cd68b2e arm/translate-a64: handle_3same_64 comment fix e961c2bee4 arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV) c177c95091 target/arm/helper: pass explicit fpst to set_rmode 71fe7953f2 target/arm/cpu.h: add additional float_status flags c2bbffe04d target/arm/cpu.h: update comment for half-precision values f5f0e3fa79 target/arm/cpu64: allow fp16 to be disabled ab954b06bc target/arm/cpu64: introduce ARM_V8_FP16 feature bit 7c3b41efe8 include/exec/helper-head.h: support f16 in helper calls === OUTPUT BEGIN === Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc' Cloning into '/var/tmp/patchew-tester-tmp-ac80g1n8/src/dtc'... Submodule path 'dtc': checked out 'e54388015af1fb4bf04d0bca99caba1074d9cc42' BUILD min-glib GEN /var/tmp/patchew-tester-tmp-ac80g1n8/src/docker-src.2018-02-08-14.15.39.4111/qemu.tar Cloning into '/var/tmp/patchew-tester-tmp-ac80g1n8/src/docker-src.2018-02-08-14.15.39.4111/qemu.tar.vroot'... done. Your branch is up-to-date with 'origin/test'. Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc' Cloning into '/var/tmp/patchew-tester-tmp-ac80g1n8/src/docker-src.2018-02-08-14.15.39.4111/qemu.tar.vroot/dtc'... Submodule path 'dtc': checked out 'e54388015af1fb4bf04d0bca99caba1074d9cc42' Submodule 'ui/keycodemapdb' (git://git.qemu.org/keycodemapdb.git) registered for path 'ui/keycodemapdb' Cloning into '/var/tmp/patchew-tester-tmp-ac80g1n8/src/docker-src.2018-02-08-14.15.39.4111/qemu.tar.vroot/ui/keycodemapdb'... Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce' COPYRUNNER RUN test-build in qemu:min-glib Environment variables: HOSTNAME=a7665e63d630 MAKEFLAGS= -j8 J=8 CCACHE_DIR=/var/tmp/ccache EXTRA_CONFIGURE_OPTS= V= SHOW_ENV=1 PATH=/usr/lib/ccache:/usr/lib64/ccache:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin PWD=/ TARGET_LIST= SHLVL=1 HOME=/root TEST_DIR=/tmp/qemu-test FEATURES= dtc DEBUG= _=/usr/bin/env Configure options: --enable-werror --target-list=x86_64-softmmu,aarch64-softmmu --prefix=/tmp/qemu-test/install No C++ compiler available; disabling C++ specific optional code Install prefix/tmp/qemu-test/install BIOS directory/tmp/qemu-test/install/share/qemu firmware path /tmp/qemu-test/install/share/qemu-firmware binary directory /tmp/qemu-test/install/bin library directory /tmp/qemu-test/install/lib module directory /tmp/qemu-test/install/lib/qemu libexec directory /tmp/qemu-test/install/libexec include directory /tmp/qemu-test/install/include config directory /tmp/qemu-test/install/etc local state directory /tmp/qemu
Re: [Qemu-devel] [PATCH v2 00/32] Add ARMv8.2 half-precision functions
Hi, This series failed docker-mingw@fedora build test. Please find the testing commands and their output below. If you have Docker installed, you can probably reproduce it locally. Type: series Message-id: 20180208173157.24705-1-alex.ben...@linaro.org Subject: [Qemu-devel] [PATCH v2 00/32] Add ARMv8.2 half-precision functions === TEST SCRIPT BEGIN === #!/bin/bash set -e git submodule update --init dtc # Let docker tests dump environment info export SHOW_ENV=1 export J=8 time make docker-test-mingw@fedora === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 Switched to a new branch 'test' 828fdf8039 arm/translate-a64: add all single op FP16 to handle_fp_1src_half bb12347df0 arm/translate-a64: implement simd_scalar_three_reg_same_fp16 9d90e658c5 arm/translate-a64: add all FP16 ops in simd_scalar_pairwise 18e4d6f1d2 arm/translate-a64: add FP16 FMOV to simd_mod_imm 487d21785a arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16 e687eee03d arm/helper.c: re-factor rsqrte and add rsqrte_f16 4078596895 arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16 14e2473a01 arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16 0080b9feb1 arm/translate-a64: add FP16 FRECPE 322031a5c9 arm/helper.c: re-factor recpe and add recepe_f16 99396effce arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16 fc0f9dbd0a arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16 ed77588f3f arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16 28b6a6a772 arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16 c8ce2f736d arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16 900561ae36 arm/translate-a64: initial decode for simd_two_reg_misc_fp16 d55f8fd2d4 arm/translate-a64: add FP16 x2 ops for simd_indexed 79200bf33e arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed eebcc3aeb6 arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16 a7d42c109d arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16 f4f8f0083b arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16 f9994103ca arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16 740b571cc7 arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16 221024b870 arm/translate-a64: initial decode for simd_three_reg_same_fp16 e55cd68b2e arm/translate-a64: handle_3same_64 comment fix e961c2bee4 arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV) c177c95091 target/arm/helper: pass explicit fpst to set_rmode 71fe7953f2 target/arm/cpu.h: add additional float_status flags c2bbffe04d target/arm/cpu.h: update comment for half-precision values f5f0e3fa79 target/arm/cpu64: allow fp16 to be disabled ab954b06bc target/arm/cpu64: introduce ARM_V8_FP16 feature bit 7c3b41efe8 include/exec/helper-head.h: support f16 in helper calls === OUTPUT BEGIN === Submodule 'dtc' (git://git.qemu-project.org/dtc.git) registered for path 'dtc' Cloning into '/var/tmp/patchew-tester-tmp-u1zn4vw2/src/dtc'... Submodule path 'dtc': checked out 'e54388015af1fb4bf04d0bca99caba1074d9cc42' BUILD fedora GEN /var/tmp/patchew-tester-tmp-u1zn4vw2/src/docker-src.2018-02-08-13.53.31.24723/qemu.tar Cloning into '/var/tmp/patchew-tester-tmp-u1zn4vw2/src/docker-src.2018-02-08-13.53.31.24723/qemu.tar.vroot'... done. Checking out files: 48% (2790/5788) Checking out files: 49% (2837/5788) Checking out files: 50% (2894/5788) Checking out files: 51% (2952/5788) Checking out files: 52% (3010/5788) Checking out files: 53% (3068/5788) Checking out files: 53% (3117/5788) Checking out files: 54% (3126/5788) Checking out files: 55% (3184/5788) Checking out files: 56% (3242/5788) Checking out files: 57% (3300/5788) Checking out files: 58% (3358/5788) Checking out files: 59% (3415/5788) Checking out files: 60% (3473/5788) Checking out files: 61% (3531/5788) Checking out files: 62% (3589/5788) Checking out files: 63% (3647/5788) Checking out files: 64% (3705/5788) Checking out files: 65% (3763/5788) Checking out files: 66% (3821/5788) Checking out files: 67% (3878/5788) Checking out files: 68% (3936/5788) Checking out files: 69% (3994/5788) Checking out files: 70% (4052/5788) Checking out files: 71% (4110/5788) Checking out files: 72% (4168/5788) Checking out files: 73% (4226/5788) Checking out files: 74% (4284/5788) Checking out files: 75% (4341/5788) Checking out files: 76% (4399/5788) Checking out files: 77% (4457/5788) Checking out files: 78% (4515/5788) Checking out files: 79% (4573/5788) Checking out files: 80% (4631/5788) Checking out files: 81% (4689/5788) Checking out files: 82% (4747/5788) Checking out files: 83% (4805/5788) Checking out files: 84% (4862/5788) Checking out files: 85% (4920/5788) Checking out files: 86% (4978/5788) Checking out files: 87% (5036/5788) Checking out files: 88% (5094
Re: [Qemu-devel] [PATCH v2 00/32] Add ARMv8.2 half-precision functions
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180208173157.24705-1-alex.ben...@linaro.org
Subject: [Qemu-devel] [PATCH v2 00/32] Add ARMv8.2 half-precision functions
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
git config --local diff.renamelimit 0
git config --local diff.renames True
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag]
patchew/20180208173157.24705-1-alex.ben...@linaro.org ->
patchew/20180208173157.24705-1-alex.ben...@linaro.org
* [new tag] patchew/20180208182223.2562-1-pbonz...@redhat.com ->
patchew/20180208182223.2562-1-pbonz...@redhat.com
Switched to a new branch 'test'
828fdf8039 arm/translate-a64: add all single op FP16 to handle_fp_1src_half
bb12347df0 arm/translate-a64: implement simd_scalar_three_reg_same_fp16
9d90e658c5 arm/translate-a64: add all FP16 ops in simd_scalar_pairwise
18e4d6f1d2 arm/translate-a64: add FP16 FMOV to simd_mod_imm
487d21785a arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16
e687eee03d arm/helper.c: re-factor rsqrte and add rsqrte_f16
4078596895 arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16
14e2473a01 arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16
0080b9feb1 arm/translate-a64: add FP16 FRECPE
322031a5c9 arm/helper.c: re-factor recpe and add recepe_f16
99396effce arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16
fc0f9dbd0a arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16
ed77588f3f arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16
28b6a6a772 arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16
c8ce2f736d arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16
900561ae36 arm/translate-a64: initial decode for simd_two_reg_misc_fp16
d55f8fd2d4 arm/translate-a64: add FP16 x2 ops for simd_indexed
79200bf33e arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed
eebcc3aeb6 arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16
a7d42c109d arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16
f4f8f0083b arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16
f9994103ca arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to
simd_three_reg_same_fp16
740b571cc7 arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to
simd_three_reg_same_fp16
221024b870 arm/translate-a64: initial decode for simd_three_reg_same_fp16
e55cd68b2e arm/translate-a64: handle_3same_64 comment fix
e961c2bee4 arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
c177c95091 target/arm/helper: pass explicit fpst to set_rmode
71fe7953f2 target/arm/cpu.h: add additional float_status flags
c2bbffe04d target/arm/cpu.h: update comment for half-precision values
f5f0e3fa79 target/arm/cpu64: allow fp16 to be disabled
ab954b06bc target/arm/cpu64: introduce ARM_V8_FP16 feature bit
7c3b41efe8 include/exec/helper-head.h: support f16 in helper calls
=== OUTPUT BEGIN ===
Checking PATCH 1/32: include/exec/helper-head.h: support f16 in helper calls...
Checking PATCH 2/32: target/arm/cpu64: introduce ARM_V8_FP16 feature bit...
Checking PATCH 3/32: target/arm/cpu64: allow fp16 to be disabled...
Checking PATCH 4/32: target/arm/cpu.h: update comment for half-precision
values...
Checking PATCH 5/32: target/arm/cpu.h: add additional float_status flags...
Checking PATCH 6/32: target/arm/helper: pass explicit fpst to set_rmode...
Checking PATCH 7/32: arm/translate-a64: implement half-precision
F(MIN|MAX)(V|NMV)...
Checking PATCH 8/32: arm/translate-a64: handle_3same_64 comment fix...
Checking PATCH 9/32: arm/translate-a64: initial decode for
simd_three_reg_same_fp16...
Checking PATCH 10/32: arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to
simd_three_reg_same_fp16...
Checking PATCH 11/32: arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to
simd_three_reg_same_fp16...
Checking PATCH 12/32: arm/translate-a64: add FP16 FMULA/X/S to
simd_three_reg_same_fp16...
Checking PATCH 13/32: arm/translate-a64: add FP16 FR[ECP/SQRT]S to
simd_three_reg_same_fp16...
Checking PATCH 14/32: arm/translate-a64: add FP16 pairwise ops
simd_three_reg_same_fp16...
Checking PATCH 15/32: arm/translate-a64: add FP16 FMULX/MLS/FMLA to
simd_indexed...
WARNING: line over 80 characters
#24: FILE: target/arm/translate-a64.c:10807:
+if (size == 1 || (size < 2 && !arm_dc_feature(s,
ARM_FEATURE_V8_FP16))) {
WARNING: line over 80 characters
#74: FILE: target/arm/translate-a64.c:10969:
+read_vec_element_i32(s
[Qemu-devel] [PATCH v2 00/32] Add ARMv8.2 half-precision functions
Hi, Some of this was posted before as part of the various partial patch series when we first started messing around with FP16 in softfloat. This series is now just the ARM bits and expects to have the V4 softfloat patches as a prerequisite: https://lists.nongnu.org/archive/html/qemu-devel/2018-02/msg01330.html Alternatively you can grab the full tree from: https://github.com/stsquad/qemu/tree/arm-fp16-v2 I've tested with the following RISU test binaries: http://people.linaro.org/~alex.bennee/testcases/arm64.risu/testcases.armv8.2_hp.tar.xz And of course I ran the original RISU tests with: -cpu any,fp16=off But I guess we really just need to carefully regenerate the testcases to not include UNDEF's which get added with future revisions of the specification. Anyway please review. Alex Bennée (32): include/exec/helper-head.h: support f16 in helper calls target/arm/cpu64: introduce ARM_V8_FP16 feature bit target/arm/cpu64: allow fp16 to be disabled target/arm/cpu.h: update comment for half-precision values target/arm/cpu.h: add additional float_status flags target/arm/helper: pass explicit fpst to set_rmode arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV) arm/translate-a64: handle_3same_64 comment fix arm/translate-a64: initial decode for simd_three_reg_same_fp16 arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16 arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16 arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16 arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16 arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16 arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed arm/translate-a64: add FP16 x2 ops for simd_indexed arm/translate-a64: initial decode for simd_two_reg_misc_fp16 arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16 arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16 arm/helper.c: re-factor recpe and add recepe_f16 arm/translate-a64: add FP16 FRECPE arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16 arm/helper.c: re-factor rsqrte and add rsqrte_f16 arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16 arm/translate-a64: add FP16 FMOV to simd_mod_imm arm/translate-a64: add all FP16 ops in simd_scalar_pairwise arm/translate-a64: implement simd_scalar_three_reg_same_fp16 arm/translate-a64: add all single op FP16 to handle_fp_1src_half include/exec/helper-head.h |3 + target/arm/cpu.h | 24 +- target/arm/cpu64.c | 28 + target/arm/helper-a64.c| 274 ++ target/arm/helper-a64.h| 34 ++ target/arm/helper.c| 466 + target/arm/helper.h| 14 +- target/arm/translate-a64.c | 1229 +--- target/arm/translate.c | 12 +- 9 files changed, 1676 insertions(+), 408 deletions(-) -- 2.15.1
