subject:"\[Qemu\-devel\] \[PATCH v2 02\/15\] ppc\/pnv\: add a PSI bridge model for POWER9"

Re: [Qemu-devel] [PATCH v2 02/15] ppc/pnv: add a PSI bridge model for POWER9

2019-03-07 Thread David Gibson

On Thu, Mar 07, 2019 at 11:35:35PM +0100, Cédric Le Goater wrote:
> The PSI bridge on POWER9 is very similar to POWER8. The BAR is still
> set through XSCOM but the controls are now entirely done with MMIOs.
> More interrupts are defined and the interrupt controller interface has
> changed to XIVE. The POWER9 model is a first example of the usage of
> the notify() handler of the XiveNotifier interface, linking the PSI
> XiveSource to its owning device model.
> 
> Signed-off-by: Cédric Le Goater 

Applied, thanks.

> ---
> 
>  Changes in v2 :
>  
>   - introduced a Pnv9Psi (XIVE) model
>   
>  include/hw/ppc/pnv.h   |   6 +
>  include/hw/ppc/pnv_psi.h   |  30 
>  include/hw/ppc/pnv_xscom.h |   3 +
>  hw/ppc/pnv.c   |  18 ++
>  hw/ppc/pnv_psi.c   | 329 -
>  5 files changed, 384 insertions(+), 2 deletions(-)
> 
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index 3b5f9cd53184..8d80cb34eebb 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -84,6 +84,7 @@ typedef struct Pnv9Chip {
>  
>  /*< public >*/
>  PnvXive  xive;
> +Pnv9Psi  psi;
>  } Pnv9Chip;
>  
>  typedef struct PnvChipClass {
> @@ -231,11 +232,16 @@ void pnv_bmc_powerdown(IPMIBmc *bmc);
>  #define PNV9_XIVE_PC_SIZE0x0010ull
>  #define PNV9_XIVE_PC_BASE(chip)  PNV9_CHIP_BASE(chip, 
> 0x00060180ull)
>  
> +#define PNV9_PSIHB_SIZE  0x0010ull
> +#define PNV9_PSIHB_BASE(chip)PNV9_CHIP_BASE(chip, 
> 0x000603020300ull)
> +
>  #define PNV9_XIVE_IC_SIZE0x0008ull
>  #define PNV9_XIVE_IC_BASE(chip)  PNV9_CHIP_BASE(chip, 
> 0x000603020310ull)
>  
>  #define PNV9_XIVE_TM_SIZE0x0004ull
>  #define PNV9_XIVE_TM_BASE(chip)  PNV9_CHIP_BASE(chip, 
> 0x000603020318ull)
>  
> +#define PNV9_PSIHB_ESB_SIZE  0x0001ull
> +#define PNV9_PSIHB_ESB_BASE(chip)PNV9_CHIP_BASE(chip, 
> 0x00060302031cull)
>  
>  #endif /* _PPC_PNV_H */
> diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h
> index 7087cbcb9ad7..2c1b27e865bd 100644
> --- a/include/hw/ppc/pnv_psi.h
> +++ b/include/hw/ppc/pnv_psi.h
> @@ -21,6 +21,7 @@
>  
>  #include "hw/sysbus.h"
>  #include "hw/ppc/xics.h"
> +#include "hw/ppc/xive.h"
>  
>  #define TYPE_PNV_PSI "pnv-psi"
>  #define PNV_PSI(obj) \
> @@ -57,6 +58,16 @@ typedef struct Pnv8Psi {
>  ICSState ics;
>  } Pnv8Psi;
>  
> +#define TYPE_PNV9_PSI TYPE_PNV_PSI "-POWER9"
> +#define PNV9_PSI(obj) \
> +OBJECT_CHECK(Pnv9Psi, (obj), TYPE_PNV9_PSI)
> +
> +typedef struct Pnv9Psi {
> +PnvPsi   parent;
> +
> +XiveSource source;
> +} Pnv9Psi;
> +
>  #define PNV_PSI_CLASS(klass) \
>   OBJECT_CLASS_CHECK(PnvPsiClass, (klass), TYPE_PNV_PSI)
>  #define PNV_PSI_GET_CLASS(obj) \
> @@ -88,4 +99,23 @@ typedef enum PnvPsiIrq {
>  
>  void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state);
>  
> +/* P9 PSI Interrupts */
> +#define PSIHB9_IRQ_PSI  0
> +#define PSIHB9_IRQ_OCC  1
> +#define PSIHB9_IRQ_FSI  2
> +#define PSIHB9_IRQ_LPCHC3
> +#define PSIHB9_IRQ_LOCAL_ERR4
> +#define PSIHB9_IRQ_GLOBAL_ERR   5
> +#define PSIHB9_IRQ_TPM  6
> +#define PSIHB9_IRQ_LPC_SIRQ07
> +#define PSIHB9_IRQ_LPC_SIRQ18
> +#define PSIHB9_IRQ_LPC_SIRQ29
> +#define PSIHB9_IRQ_LPC_SIRQ310
> +#define PSIHB9_IRQ_SBE_I2C  11
> +#define PSIHB9_IRQ_DIO  12
> +#define PSIHB9_IRQ_PSU  13
> +#define PSIHB9_NUM_IRQS 14
> +
> +void pnv_psi_pic_print_info(Pnv9Psi *psi, Monitor *mon);
> +
>  #endif /* _PPC_PNV_PSI_H */
> diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
> index 6623ec54a7a8..403a365ed274 100644
> --- a/include/hw/ppc/pnv_xscom.h
> +++ b/include/hw/ppc/pnv_xscom.h
> @@ -73,6 +73,9 @@ typedef struct PnvXScomInterfaceClass {
>  #define PNV_XSCOM_OCC_BASE0x0066000
>  #define PNV_XSCOM_OCC_SIZE0x6000
>  
> +#define PNV9_XSCOM_PSIHB_BASE 0x5012900
> +#define PNV9_XSCOM_PSIHB_SIZE 0x100
> +
>  #define PNV9_XSCOM_XIVE_BASE  0x5013000
>  #define PNV9_XSCOM_XIVE_SIZE  0x300
>  
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 5bb2332f167a..1cc454cbbc27 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -579,6 +579,7 @@ static void pnv_chip_power9_pic_print_info(PnvChip *chip, 
> Monitor *mon)
>  Pnv9Chip *chip9 = PNV9_CHIP(chip);
>  
>  pnv_xive_pic_print_info(>xive, mon);
> +pnv_psi_pic_print_info(>psi, mon);
>  }
>  
>  static void pnv_init(MachineState *machine)
> @@ -950,6 +951,11 @@ static void pnv_chip_power9_instance_init(Object *obj)
>  TYPE_PNV_XIVE, _abort, NULL);
>  object_property_add_const_link(OBJECT(>xive), "chip", obj,
> _abort);
> +
> +object_initialize_child(obj, "psi",  >psi, sizeof(chip9->psi),
> +TYPE_PNV9_PSI, _abort, NULL);
> +

[Qemu-devel] [PATCH v2 02/15] ppc/pnv: add a PSI bridge model for POWER9

2019-03-07 Thread Cédric Le Goater

The PSI bridge on POWER9 is very similar to POWER8. The BAR is still
set through XSCOM but the controls are now entirely done with MMIOs.
More interrupts are defined and the interrupt controller interface has
changed to XIVE. The POWER9 model is a first example of the usage of
the notify() handler of the XiveNotifier interface, linking the PSI
XiveSource to its owning device model.

Signed-off-by: Cédric Le Goater 
---

 Changes in v2 :
 
  - introduced a Pnv9Psi (XIVE) model
  
 include/hw/ppc/pnv.h   |   6 +
 include/hw/ppc/pnv_psi.h   |  30 
 include/hw/ppc/pnv_xscom.h |   3 +
 hw/ppc/pnv.c   |  18 ++
 hw/ppc/pnv_psi.c   | 329 -
 5 files changed, 384 insertions(+), 2 deletions(-)

diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 3b5f9cd53184..8d80cb34eebb 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -84,6 +84,7 @@ typedef struct Pnv9Chip {
 
 /*< public >*/
 PnvXive  xive;
+Pnv9Psi  psi;
 } Pnv9Chip;
 
 typedef struct PnvChipClass {
@@ -231,11 +232,16 @@ void pnv_bmc_powerdown(IPMIBmc *bmc);
 #define PNV9_XIVE_PC_SIZE0x0010ull
 #define PNV9_XIVE_PC_BASE(chip)  PNV9_CHIP_BASE(chip, 
0x00060180ull)
 
+#define PNV9_PSIHB_SIZE  0x0010ull
+#define PNV9_PSIHB_BASE(chip)PNV9_CHIP_BASE(chip, 
0x000603020300ull)
+
 #define PNV9_XIVE_IC_SIZE0x0008ull
 #define PNV9_XIVE_IC_BASE(chip)  PNV9_CHIP_BASE(chip, 
0x000603020310ull)
 
 #define PNV9_XIVE_TM_SIZE0x0004ull
 #define PNV9_XIVE_TM_BASE(chip)  PNV9_CHIP_BASE(chip, 
0x000603020318ull)
 
+#define PNV9_PSIHB_ESB_SIZE  0x0001ull
+#define PNV9_PSIHB_ESB_BASE(chip)PNV9_CHIP_BASE(chip, 
0x00060302031cull)
 
 #endif /* _PPC_PNV_H */
diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h
index 7087cbcb9ad7..2c1b27e865bd 100644
--- a/include/hw/ppc/pnv_psi.h
+++ b/include/hw/ppc/pnv_psi.h
@@ -21,6 +21,7 @@
 
 #include "hw/sysbus.h"
 #include "hw/ppc/xics.h"
+#include "hw/ppc/xive.h"
 
 #define TYPE_PNV_PSI "pnv-psi"
 #define PNV_PSI(obj) \
@@ -57,6 +58,16 @@ typedef struct Pnv8Psi {
 ICSState ics;
 } Pnv8Psi;
 
+#define TYPE_PNV9_PSI TYPE_PNV_PSI "-POWER9"
+#define PNV9_PSI(obj) \
+OBJECT_CHECK(Pnv9Psi, (obj), TYPE_PNV9_PSI)
+
+typedef struct Pnv9Psi {
+PnvPsi   parent;
+
+XiveSource source;
+} Pnv9Psi;
+
 #define PNV_PSI_CLASS(klass) \
  OBJECT_CLASS_CHECK(PnvPsiClass, (klass), TYPE_PNV_PSI)
 #define PNV_PSI_GET_CLASS(obj) \
@@ -88,4 +99,23 @@ typedef enum PnvPsiIrq {
 
 void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state);
 
+/* P9 PSI Interrupts */
+#define PSIHB9_IRQ_PSI  0
+#define PSIHB9_IRQ_OCC  1
+#define PSIHB9_IRQ_FSI  2
+#define PSIHB9_IRQ_LPCHC3
+#define PSIHB9_IRQ_LOCAL_ERR4
+#define PSIHB9_IRQ_GLOBAL_ERR   5
+#define PSIHB9_IRQ_TPM  6
+#define PSIHB9_IRQ_LPC_SIRQ07
+#define PSIHB9_IRQ_LPC_SIRQ18
+#define PSIHB9_IRQ_LPC_SIRQ29
+#define PSIHB9_IRQ_LPC_SIRQ310
+#define PSIHB9_IRQ_SBE_I2C  11
+#define PSIHB9_IRQ_DIO  12
+#define PSIHB9_IRQ_PSU  13
+#define PSIHB9_NUM_IRQS 14
+
+void pnv_psi_pic_print_info(Pnv9Psi *psi, Monitor *mon);
+
 #endif /* _PPC_PNV_PSI_H */
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index 6623ec54a7a8..403a365ed274 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -73,6 +73,9 @@ typedef struct PnvXScomInterfaceClass {
 #define PNV_XSCOM_OCC_BASE0x0066000
 #define PNV_XSCOM_OCC_SIZE0x6000
 
+#define PNV9_XSCOM_PSIHB_BASE 0x5012900
+#define PNV9_XSCOM_PSIHB_SIZE 0x100
+
 #define PNV9_XSCOM_XIVE_BASE  0x5013000
 #define PNV9_XSCOM_XIVE_SIZE  0x300
 
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 5bb2332f167a..1cc454cbbc27 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -579,6 +579,7 @@ static void pnv_chip_power9_pic_print_info(PnvChip *chip, 
Monitor *mon)
 Pnv9Chip *chip9 = PNV9_CHIP(chip);
 
 pnv_xive_pic_print_info(>xive, mon);
+pnv_psi_pic_print_info(>psi, mon);
 }
 
 static void pnv_init(MachineState *machine)
@@ -950,6 +951,11 @@ static void pnv_chip_power9_instance_init(Object *obj)
 TYPE_PNV_XIVE, _abort, NULL);
 object_property_add_const_link(OBJECT(>xive), "chip", obj,
_abort);
+
+object_initialize_child(obj, "psi",  >psi, sizeof(chip9->psi),
+TYPE_PNV9_PSI, _abort, NULL);
+object_property_add_const_link(OBJECT(>psi), "chip", obj,
+   _abort);
 }
 
 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
@@ -957,6 +963,7 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error 
**errp)
 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
 Pnv9Chip *chip9 = PNV9_CHIP(dev);
 PnvChip *chip

Re: [Qemu-devel] [PATCH v2 02/15] ppc/pnv: add a PSI bridge model for POWER9

[Qemu-devel] [PATCH v2 02/15] ppc/pnv: add a PSI bridge model for POWER9

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