Re: [Qemu-devel] [PATCH v2 06/15] ppc/pnv: add a LPC Controller model for POWER9

[David Gibson]

On Thu, Mar 07, 2019 at 11:35:39PM +0100, Cédric Le Goater wrote:
> The LPC Controller on POWER9 is very similar to the one found on
> POWER8 but accesses are now done via on MMIOs, without the XSCOM and
> ECCB logic. The device tree is populated differently so we add a
> specific POWER9 routine for the purpose.
> 
> SerIRQ routing is yet to be done.
> 
> Signed-off-by: Cédric Le Goater 

[snip]
> +static uint64_t pnv_lpc_mmio_read(void *opaque, hwaddr addr, unsigned size)
> +{
> +PnvLpcController *lpc = PNV_LPC(opaque);
> +uint64_t val = 0;
> +uint32_t opb_addr = addr & ECCB_CTL_ADDR_MASK;
> +MemTxResult result;
> +
> +switch (size) {
> +case 4:
> +val = address_space_ldl(>opb_as, opb_addr, 
> MEMTXATTRS_UNSPECIFIED,
> +);

This extra level of indirection via the opb_as still seems very
dubious to me.  But I guess it's something we can fix later, so,
applied.


> +break;
> +case 1:
> +val = address_space_ldub(>opb_as, opb_addr, 
> MEMTXATTRS_UNSPECIFIED,
> + );
> +break;
> +default:
> +qemu_log_mask(LOG_GUEST_ERROR, "OPB read failed at @0x%"
> +  HWADDR_PRIx " invalid size %d\n", addr, size);
> +return 0;
> +}
> +
> +if (result != MEMTX_OK) {
> +qemu_log_mask(LOG_GUEST_ERROR, "OPB read failed at @0x%"
> +  HWADDR_PRIx "\n", addr);
> +}
> +
> +return val;
> +}
> +
> +static void pnv_lpc_mmio_write(void *opaque, hwaddr addr,
> +uint64_t val, unsigned size)
> +{
> +PnvLpcController *lpc = PNV_LPC(opaque);
> +uint32_t opb_addr = addr & ECCB_CTL_ADDR_MASK;
> +MemTxResult result;
> +
> +switch (size) {
> +case 4:
> +address_space_stl(>opb_as, opb_addr, val, 
> MEMTXATTRS_UNSPECIFIED,
> +  );
> + break;
> +case 1:
> +address_space_stb(>opb_as, opb_addr, val, 
> MEMTXATTRS_UNSPECIFIED,
> +  );
> +break;
> +default:
> +qemu_log_mask(LOG_GUEST_ERROR, "OPB write failed at @0x%"
> +  HWADDR_PRIx " invalid size %d\n", addr, size);
> +return;
> +}
> +
> +if (result != MEMTX_OK) {
> +qemu_log_mask(LOG_GUEST_ERROR, "OPB write failed at @0x%"
> +  HWADDR_PRIx "\n", addr);
> +}
> +}
> +
> +static const MemoryRegionOps pnv_lpc_mmio_ops = {
> +.read = pnv_lpc_mmio_read,
> +.write = pnv_lpc_mmio_write,
> +.impl = {
> +.min_access_size = 1,
> +.max_access_size = 4,
> +},
> +.endianness = DEVICE_BIG_ENDIAN,
> +};
> +
>  static void pnv_lpc_eval_irqs(PnvLpcController *lpc)
>  {
>  bool lpc_to_opb_irq = false;
> @@ -465,6 +627,43 @@ static const TypeInfo pnv_lpc_power8_info = {
>  }
>  };
>  
> +static void pnv_lpc_power9_realize(DeviceState *dev, Error **errp)
> +{
> +PnvLpcController *lpc = PNV_LPC(dev);
> +PnvLpcClass *plc = PNV_LPC_GET_CLASS(dev);
> +Error *local_err = NULL;
> +
> +plc->parent_realize(dev, _err);
> +if (local_err) {
> +error_propagate(errp, local_err);
> +return;
> +}
> +
> +/* P9 uses a MMIO region */
> +memory_region_init_io(>xscom_regs, OBJECT(lpc), _lpc_mmio_ops,
> +  lpc, "lpcm", PNV9_LPCM_SIZE);
> +}
> +
> +static void pnv_lpc_power9_class_init(ObjectClass *klass, void *data)
> +{
> +DeviceClass *dc = DEVICE_CLASS(klass);
> +PnvLpcClass *plc = PNV_LPC_CLASS(klass);
> +
> +dc->desc = "PowerNV LPC Controller POWER9";
> +
> +plc->psi_irq = PSIHB9_IRQ_LPCHC;
> +
> +device_class_set_parent_realize(dc, pnv_lpc_power9_realize,
> +>parent_realize);
> +}
> +
> +static const TypeInfo pnv_lpc_power9_info = {
> +.name  = TYPE_PNV9_LPC,
> +.parent= TYPE_PNV_LPC,
> +.instance_size = sizeof(PnvLpcController),
> +.class_init= pnv_lpc_power9_class_init,
> +};
> +
>  static void pnv_lpc_realize(DeviceState *dev, Error **errp)
>  {
>  PnvLpcController *lpc = PNV_LPC(dev);
> @@ -540,6 +739,7 @@ static void pnv_lpc_register_types(void)
>  {
>  type_register_static(_lpc_info);
>  type_register_static(_lpc_power8_info);
> +type_register_static(_lpc_power9_info);
>  }
>  
>  type_init(pnv_lpc_register_types)

-- 
David Gibson| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson


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[Qemu-devel] [PATCH v2 06/15] ppc/pnv: add a LPC Controller model for POWER9

[Cédric Le Goater]

The LPC Controller on POWER9 is very similar to the one found on
POWER8 but accesses are now done via on MMIOs, without the XSCOM and
ECCB logic. The device tree is populated differently so we add a
specific POWER9 routine for the purpose.

SerIRQ routing is yet to be done.

Signed-off-by: Cédric Le Goater 
---

 Changes in v2:

 - defined a 'dt_isa_nodename' for the POWER9 chip

 include/hw/ppc/pnv.h |   4 +
 include/hw/ppc/pnv_lpc.h |   9 ++
 hw/ppc/pnv.c |  22 -
 hw/ppc/pnv_lpc.c | 200 +++
 4 files changed, 234 insertions(+), 1 deletion(-)

diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index c81f157f41a9..1cd1ad622d0b 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -87,6 +87,7 @@ typedef struct Pnv9Chip {
 /*< public >*/
 PnvXive  xive;
 Pnv9Psi  psi;
+PnvLpcController lpc;
 } Pnv9Chip;
 
 typedef struct PnvChipClass {
@@ -234,6 +235,9 @@ void pnv_bmc_powerdown(IPMIBmc *bmc);
 #define PNV9_XIVE_PC_SIZE0x0010ull
 #define PNV9_XIVE_PC_BASE(chip)  PNV9_CHIP_BASE(chip, 
0x00060180ull)
 
+#define PNV9_LPCM_SIZE   0x0001ull
+#define PNV9_LPCM_BASE(chip) PNV9_CHIP_BASE(chip, 
0x00060300ull)
+
 #define PNV9_PSIHB_SIZE  0x0010ull
 #define PNV9_PSIHB_BASE(chip)PNV9_CHIP_BASE(chip, 
0x000603020300ull)
 
diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h
index f3f24419b19a..242b18081caa 100644
--- a/include/hw/ppc/pnv_lpc.h
+++ b/include/hw/ppc/pnv_lpc.h
@@ -27,6 +27,9 @@
 #define TYPE_PNV8_LPC TYPE_PNV_LPC "-POWER8"
 #define PNV8_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV8_LPC)
 
+#define TYPE_PNV9_LPC TYPE_PNV_LPC "-POWER9"
+#define PNV9_LPC(obj) OBJECT_CHECK(PnvLpcController, (obj), TYPE_PNV9_LPC)
+
 typedef struct PnvLpcController {
 DeviceState parent;
 
@@ -85,6 +88,12 @@ typedef struct PnvLpcClass {
 DeviceRealize parent_realize;
 } PnvLpcClass;
 
+/*
+ * Old compilers error on typdef forward declarations. Keep them happy.
+ */
+struct PnvChip;
+
 ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp);
+int pnv_dt_lpc(struct PnvChip *chip, void *fdt, int root_offset);
 
 #endif /* _PPC_PNV_LPC_H */
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 6625562d276d..918fae057b5c 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -306,6 +306,8 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, void 
*fdt)
 if (chip->ram_size) {
 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
 }
+
+pnv_dt_lpc(chip, fdt, 0);
 }
 
 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
@@ -547,7 +549,8 @@ static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, 
Error **errp)
 
 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
 {
-return NULL;
+Pnv9Chip *chip9 = PNV9_CHIP(chip);
+return pnv_lpc_isa_create(>lpc, false, errp);
 }
 
 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
@@ -948,6 +951,11 @@ static void pnv_chip_power9_instance_init(Object *obj)
 TYPE_PNV9_PSI, _abort, NULL);
 object_property_add_const_link(OBJECT(>psi), "chip", obj,
_abort);
+
+object_initialize_child(obj, "lpc",  >lpc, sizeof(chip9->lpc),
+TYPE_PNV9_LPC, _abort, NULL);
+object_property_add_const_link(OBJECT(>lpc), "psi",
+   OBJECT(>psi), _abort);
 }
 
 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
@@ -992,6 +1000,18 @@ static void pnv_chip_power9_realize(DeviceState *dev, 
Error **errp)
 }
 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
 _PSI(psi9)->xscom_regs);
+
+/* LPC */
+object_property_set_bool(OBJECT(>lpc), true, "realized", 
_err);
+if (local_err) {
+error_propagate(errp, local_err);
+return;
+}
+memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
+>lpc.xscom_regs);
+
+chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
+(uint64_t) PNV9_LPCM_BASE(chip));
 }
 
 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index 3c509a30a0af..6df694e0abc1 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -118,6 +118,100 @@ static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, void 
*fdt, int xscom_offset)
 return 0;
 }
 
+/* POWER9 only */
+int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset)
+{
+const char compat[] = "ibm,power9-lpcm-opb\0simple-bus";
+const char lpc_compat[] = "ibm,power9-lpc\0ibm,lpc";
+char *name;
+int offset, lpcm_offset;
+uint64_t lpcm_addr = PNV9_LPCM_BASE(chip);
+uint32_t opb_ranges[8] = { 0,
+