Re: [Qemu-devel] [PATCH v2 1/4] ppc/pnv: introduce a new intc_create() operation to the chip model
On Fri, Jun 15, 2018 at 05:25:33PM +0200, Cédric Le Goater wrote:
> On Power9, the thread interrupt presenter has a different type and is
> linked to the chip owning the cores.
>
> Signed-off-by: Cédric Le Goater
Applied to ppc-for-3.0, thanks.
> ---
> include/hw/ppc/pnv.h | 1 +
> hw/ppc/pnv.c | 21 +++--
> hw/ppc/pnv_core.c| 18 +-
> 3 files changed, 29 insertions(+), 11 deletions(-)
>
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index 90759240a7b1..e934e84f555e 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -76,6 +76,7 @@ typedef struct PnvChipClass {
> hwaddr xscom_base;
>
> uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
> +Object *(*intc_create)(PnvChip *chip, Object *child, Error **errp);
> } PnvChipClass;
>
> #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
> index 0d2b79f7980f..c7e127ae97db 100644
> --- a/hw/ppc/pnv.c
> +++ b/hw/ppc/pnv.c
> @@ -671,6 +671,13 @@ static uint32_t pnv_chip_core_pir_p8(PnvChip *chip,
> uint32_t core_id)
> return (chip->chip_id << 7) | (core_id << 3);
> }
>
> +static Object *pnv_chip_power8_intc_create(PnvChip *chip, Object *child,
> + Error **errp)
> +{
> +return icp_create(child, TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()),
> + errp);
> +}
> +
> /*
> *0:48 Reserved - Read as zeroes
> * 49:52 Node ID
> @@ -686,6 +693,12 @@ static uint32_t pnv_chip_core_pir_p9(PnvChip *chip,
> uint32_t core_id)
> return (chip->chip_id << 8) | (core_id << 2);
> }
>
> +static Object *pnv_chip_power9_intc_create(PnvChip *chip, Object *child,
> + Error **errp)
> +{
> +return NULL;
> +}
> +
> /* Allowed core identifiers on a POWER8 Processor Chip :
> *
> *
> @@ -721,6 +734,7 @@ static void pnv_chip_power8e_class_init(ObjectClass
> *klass, void *data)
> k->chip_cfam_id = 0x221ef0498000ull; /* P8 Murano DD2.1 */
> k->cores_mask = POWER8E_CORE_MASK;
> k->core_pir = pnv_chip_core_pir_p8;
> +k->intc_create = pnv_chip_power8_intc_create;
> k->xscom_base = 0x003fc00ull;
> dc->desc = "PowerNV Chip POWER8E";
> }
> @@ -734,6 +748,7 @@ static void pnv_chip_power8_class_init(ObjectClass
> *klass, void *data)
> k->chip_cfam_id = 0x220ea0498000ull; /* P8 Venice DD2.0 */
> k->cores_mask = POWER8_CORE_MASK;
> k->core_pir = pnv_chip_core_pir_p8;
> +k->intc_create = pnv_chip_power8_intc_create;
> k->xscom_base = 0x003fc00ull;
> dc->desc = "PowerNV Chip POWER8";
> }
> @@ -747,6 +762,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass
> *klass, void *data)
> k->chip_cfam_id = 0x120d30498000ull; /* P8 Naples DD1.0 */
> k->cores_mask = POWER8_CORE_MASK;
> k->core_pir = pnv_chip_core_pir_p8;
> +k->intc_create = pnv_chip_power8_intc_create;
> k->xscom_base = 0x003fc00ull;
> dc->desc = "PowerNV Chip POWER8NVL";
> }
> @@ -760,6 +776,7 @@ static void pnv_chip_power9_class_init(ObjectClass
> *klass, void *data)
> k->chip_cfam_id = 0x220d10498000ull; /* P9 Nimbus DD2.0 */
> k->cores_mask = POWER9_CORE_MASK;
> k->core_pir = pnv_chip_core_pir_p9;
> +k->intc_create = pnv_chip_power9_intc_create;
> k->xscom_base = 0x00603fcull;
> dc->desc = "PowerNV Chip POWER9";
> }
> @@ -892,8 +909,8 @@ static void pnv_chip_core_realize(PnvChip *chip, Error
> **errp)
> object_property_set_int(OBJECT(pnv_core),
> pcc->core_pir(chip, core_hwid),
> "pir", _fatal);
> -object_property_add_const_link(OBJECT(pnv_core), "xics",
> - qdev_get_machine(), _fatal);
> +object_property_add_const_link(OBJECT(pnv_core), "chip",
> + OBJECT(chip), _fatal);
> object_property_set_bool(OBJECT(pnv_core), true, "realized",
> _fatal);
> object_unref(OBJECT(pnv_core));
> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
> index f7cf33f547a5..a9f129fc2c5f 100644
> --- a/hw/ppc/pnv_core.c
> +++ b/hw/ppc/pnv_core.c
> @@ -99,13 +99,14 @@ static const MemoryRegionOps pnv_core_xscom_ops = {
> .endianness = DEVICE_BIG_ENDIAN,
> };
>
> -static void pnv_realize_vcpu(PowerPCCPU *cpu, XICSFabric *xi, Error **errp)
> +static void pnv_realize_vcpu(PowerPCCPU *cpu, PnvChip *chip, Error **errp)
> {
> CPUPPCState *env = >env;
> int core_pir;
> int thread_index = 0; /* TODO: TCG supports only one thread */
> ppc_spr_t *pir = >spr_cb[SPR_PIR];
> Error *local_err = NULL;
> +PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
>
> object_property_set_bool(OBJECT(cpu), true, "realized", _err);
> if (local_err) {
> @@ -113,7 +114,7 @@
[Qemu-devel] [PATCH v2 1/4] ppc/pnv: introduce a new intc_create() operation to the chip model
On Power9, the thread interrupt presenter has a different type and is
linked to the chip owning the cores.
Signed-off-by: Cédric Le Goater
---
include/hw/ppc/pnv.h | 1 +
hw/ppc/pnv.c | 21 +++--
hw/ppc/pnv_core.c| 18 +-
3 files changed, 29 insertions(+), 11 deletions(-)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 90759240a7b1..e934e84f555e 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -76,6 +76,7 @@ typedef struct PnvChipClass {
hwaddr xscom_base;
uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
+Object *(*intc_create)(PnvChip *chip, Object *child, Error **errp);
} PnvChipClass;
#define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 0d2b79f7980f..c7e127ae97db 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -671,6 +671,13 @@ static uint32_t pnv_chip_core_pir_p8(PnvChip *chip,
uint32_t core_id)
return (chip->chip_id << 7) | (core_id << 3);
}
+static Object *pnv_chip_power8_intc_create(PnvChip *chip, Object *child,
+ Error **errp)
+{
+return icp_create(child, TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()),
+ errp);
+}
+
/*
*0:48 Reserved - Read as zeroes
* 49:52 Node ID
@@ -686,6 +693,12 @@ static uint32_t pnv_chip_core_pir_p9(PnvChip *chip,
uint32_t core_id)
return (chip->chip_id << 8) | (core_id << 2);
}
+static Object *pnv_chip_power9_intc_create(PnvChip *chip, Object *child,
+ Error **errp)
+{
+return NULL;
+}
+
/* Allowed core identifiers on a POWER8 Processor Chip :
*
*
@@ -721,6 +734,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass,
void *data)
k->chip_cfam_id = 0x221ef0498000ull; /* P8 Murano DD2.1 */
k->cores_mask = POWER8E_CORE_MASK;
k->core_pir = pnv_chip_core_pir_p8;
+k->intc_create = pnv_chip_power8_intc_create;
k->xscom_base = 0x003fc00ull;
dc->desc = "PowerNV Chip POWER8E";
}
@@ -734,6 +748,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass,
void *data)
k->chip_cfam_id = 0x220ea0498000ull; /* P8 Venice DD2.0 */
k->cores_mask = POWER8_CORE_MASK;
k->core_pir = pnv_chip_core_pir_p8;
+k->intc_create = pnv_chip_power8_intc_create;
k->xscom_base = 0x003fc00ull;
dc->desc = "PowerNV Chip POWER8";
}
@@ -747,6 +762,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass
*klass, void *data)
k->chip_cfam_id = 0x120d30498000ull; /* P8 Naples DD1.0 */
k->cores_mask = POWER8_CORE_MASK;
k->core_pir = pnv_chip_core_pir_p8;
+k->intc_create = pnv_chip_power8_intc_create;
k->xscom_base = 0x003fc00ull;
dc->desc = "PowerNV Chip POWER8NVL";
}
@@ -760,6 +776,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass,
void *data)
k->chip_cfam_id = 0x220d10498000ull; /* P9 Nimbus DD2.0 */
k->cores_mask = POWER9_CORE_MASK;
k->core_pir = pnv_chip_core_pir_p9;
+k->intc_create = pnv_chip_power9_intc_create;
k->xscom_base = 0x00603fcull;
dc->desc = "PowerNV Chip POWER9";
}
@@ -892,8 +909,8 @@ static void pnv_chip_core_realize(PnvChip *chip, Error
**errp)
object_property_set_int(OBJECT(pnv_core),
pcc->core_pir(chip, core_hwid),
"pir", _fatal);
-object_property_add_const_link(OBJECT(pnv_core), "xics",
- qdev_get_machine(), _fatal);
+object_property_add_const_link(OBJECT(pnv_core), "chip",
+ OBJECT(chip), _fatal);
object_property_set_bool(OBJECT(pnv_core), true, "realized",
_fatal);
object_unref(OBJECT(pnv_core));
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index f7cf33f547a5..a9f129fc2c5f 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -99,13 +99,14 @@ static const MemoryRegionOps pnv_core_xscom_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static void pnv_realize_vcpu(PowerPCCPU *cpu, XICSFabric *xi, Error **errp)
+static void pnv_realize_vcpu(PowerPCCPU *cpu, PnvChip *chip, Error **errp)
{
CPUPPCState *env = >env;
int core_pir;
int thread_index = 0; /* TODO: TCG supports only one thread */
ppc_spr_t *pir = >spr_cb[SPR_PIR];
Error *local_err = NULL;
+PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
object_property_set_bool(OBJECT(cpu), true, "realized", _err);
if (local_err) {
@@ -113,7 +114,7 @@ static void pnv_realize_vcpu(PowerPCCPU *cpu, XICSFabric
*xi, Error **errp)
return;
}
-cpu->intc = icp_create(OBJECT(cpu), TYPE_PNV_ICP, xi, _err);
+cpu->intc = pcc->intc_create(chip, OBJECT(cpu), _err);
if (local_err) {
error_propagate(errp, local_err);
return;
@@ -143,13 +144,12 @@ static void
