Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
On 10 February 2014 15:42, Peter Maydell peter.mayd...@linaro.org wrote:
On 10 February 2014 13:51, Andreas Färber afaer...@suse.de wrote:
Am 24.01.2014 17:18, schrieb Petar Jovanovic:
From: Petar Jovanovic petar.jovano...@imgtec.com
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -333,6 +333,31 @@ static const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
.mmu_type = MMU_TYPE_R4000,
},
+{
+/* A generic CPU providing MIPS32 Release 5 features.
+ FIXME: Eventually this should be replaced by a real CPU model.
*/
That is not really possible. QEMU needs to keep command line backwards
compatibility, so if you add a generic model now, we will need to live
with the generic model for a long time. What's the difficulty with
taking a real CPU model? Is there no silicon yet or just a code name
rather than a marketing name?
Good point, though I notice we have two MIPS CPUs already
with this same 'FIXME' comment about being generic.
So before I apply the pull request with this patch, does
anybody want to actually object to adding another 'generic'
MIPS CPU to the two we have already? It seems reasonable
enough to me.
thanks
-- PMM
Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
Am 13.02.2014 15:51, schrieb Peter Maydell:
On 10 February 2014 15:42, Peter Maydell peter.mayd...@linaro.org wrote:
On 10 February 2014 13:51, Andreas Färber afaer...@suse.de wrote:
Am 24.01.2014 17:18, schrieb Petar Jovanovic:
From: Petar Jovanovic petar.jovano...@imgtec.com
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -333,6 +333,31 @@ static const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
.mmu_type = MMU_TYPE_R4000,
},
+{
+/* A generic CPU providing MIPS32 Release 5 features.
+ FIXME: Eventually this should be replaced by a real CPU model.
*/
That is not really possible. QEMU needs to keep command line backwards
compatibility, so if you add a generic model now, we will need to live
with the generic model for a long time. What's the difficulty with
taking a real CPU model? Is there no silicon yet or just a code name
rather than a marketing name?
Good point, though I notice we have two MIPS CPUs already
with this same 'FIXME' comment about being generic.
So before I apply the pull request with this patch, does
anybody want to actually object to adding another 'generic'
MIPS CPU to the two we have already? It seems reasonable
enough to me.
No objection from my side. I was however expecting Petar to drop the
FIXME in response to my reply, which I believe was still in the PULL.
Peter, are you planning (or did I miss) a follow-up cleaning that up,
whether for your new model or for all?
Regards,
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
From: Andreas Färber [afaer...@suse.de] Sent: Thursday, February 13, 2014 5:11 PM To: Peter Maydell; Petar Jovanovic Cc: QEMU Developers; Petar Jovanovic; Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5 No objection from my side. I was however expecting Petar to drop the FIXME in response to my reply, which I believe was still in the PULL. Peter, are you planning (or did I miss) a follow-up cleaning that up, whether for your new model or for all? I would leave this FIXME, since we need to fix at least .CP0_PRid value once the real silicon is available, because it will have to match value known to kernel at that time. As for other FIXMEs in the same file, I would change that in a separate patch later. I do plan to update this area more, with additional 5KEc and 5KEf models. Regards, Petar
Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
ping
http://patchwork.ozlabs.org/patch/313937/
http://patchwork.ozlabs.org/patch/313938/
http://patchwork.ozlabs.org/patch/313944/
http://patchwork.ozlabs.org/patch/313936/
From: Petar Jovanovic
Sent: Tuesday, February 04, 2014 2:59 PM
To: Petar Jovanovic; qemu-devel@nongnu.org
Cc: aurel...@aurel32.net
Subject: RE: [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
ping
http://patchwork.ozlabs.org/patch/313937/
http://patchwork.ozlabs.org/patch/313938/
http://patchwork.ozlabs.org/patch/313944/
http://patchwork.ozlabs.org/patch/313936/
Regards,
Petar
From: Petar Jovanovic [petar.jovano...@rt-rk.com]
Sent: Friday, January 24, 2014 5:18 PM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurel...@aurel32.net
Subject: [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
From: Petar Jovanovic petar.jovano...@imgtec.com
Add mips32r5-generic among CPU definitions for MIPS.
Define ISA_MIPS32R3 and ISA_MIPS32R5.
Signed-off-by: Petar Jovanovic petar.jovano...@imgtec.com
---
target-mips/mips-defs.h |8
target-mips/translate_init.c | 25 +
2 files changed, 33 insertions(+)
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index bf094a3..9dfa516 100644
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -29,6 +29,8 @@
#defineISA_MIPS32R20x0040
#defineISA_MIPS64 0x0080
#defineISA_MIPS64R20x0100
+#define ISA_MIPS32R3 0x0200
+#define ISA_MIPS32R5 0x0400
/* MIPS ASEs. */
#defineASE_MIPS16 0x1000
@@ -64,6 +66,12 @@
#defineCPU_MIPS32R2(CPU_MIPS32 | ISA_MIPS32R2)
#defineCPU_MIPS64R2(CPU_MIPS64 | CPU_MIPS32R2 |
ISA_MIPS64R2)
+/* MIPS Technologies Release 3 */
+#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
+
+/* MIPS Technologies Release 5 */
+#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
+
/* Strictly follow the architecture standard:
- Disallow special instruction handling for PMON/SPIM.
Note that we still maintain Count/Compare to match the host clock. */
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c45b1b2..d74a0af 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -333,6 +333,31 @@ static const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
.mmu_type = MMU_TYPE_R4000,
},
+{
+/* A generic CPU providing MIPS32 Release 5 features.
+ FIXME: Eventually this should be replaced by a real CPU model. */
+.name = mips32r5-generic,
+.CP0_PRid = 0x00019700,
+.CP0_Config0 = MIPS_CONFIG0 | (0x1 CP0C0_AR) |
+(MMU_TYPE_R4000 CP0C0_MT),
+.CP0_Config1 = MIPS_CONFIG1 | (1 CP0C1_FP) | (15 CP0C1_MMU) |
+ (0 CP0C1_IS) | (3 CP0C1_IL) | (1 CP0C1_IA) |
+ (0 CP0C1_DS) | (3 CP0C1_DL) | (1 CP0C1_DA) |
+ (1 CP0C1_CA),
+.CP0_Config2 = MIPS_CONFIG2,
+.CP0_Config3 = MIPS_CONFIG3,
+.CP0_LLAddr_rw_bitmask = 0,
+.CP0_LLAddr_shift = 4,
+.SYNCI_Step = 32,
+.CCRes = 2,
+.CP0_Status_rw_bitmask = 0x3778FF1F,
+.CP1_fcr0 = (1 FCR0_F64) | (1 FCR0_L) | (1 FCR0_W) |
+(1 FCR0_D) | (1 FCR0_S) | (0x93 FCR0_PRID),
+.SEGBITS = 32,
+.PABITS = 32,
+.insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
+.mmu_type = MMU_TYPE_R4000,
+},
#if defined(TARGET_MIPS64)
{
.name = R4000,
--
1.7.9.5
Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
On 10 February 2014 11:21, Petar Jovanovic petar.jovano...@imgtec.com wrote: ping http://patchwork.ozlabs.org/patch/313937/ http://patchwork.ozlabs.org/patch/313938/ http://patchwork.ozlabs.org/patch/313944/ http://patchwork.ozlabs.org/patch/313936/ These look reasonably sane to me on a quick glance. So, in the interests of not stalling MIPS target development indefinitely, I suggest you gather up these patches (and any other small 'lost' MIPS patches which have got code review), make sure they have the right Reviewed-by: and signed-off-by tags on them, and put them into a pull request. thanks -- PMM
Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
Am 24.01.2014 17:18, schrieb Petar Jovanovic:
From: Petar Jovanovic petar.jovano...@imgtec.com
Add mips32r5-generic among CPU definitions for MIPS.
Define ISA_MIPS32R3 and ISA_MIPS32R5.
Signed-off-by: Petar Jovanovic petar.jovano...@imgtec.com
---
target-mips/mips-defs.h |8
target-mips/translate_init.c | 25 +
2 files changed, 33 insertions(+)
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index bf094a3..9dfa516 100644
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -29,6 +29,8 @@
#define ISA_MIPS32R20x0040
#define ISA_MIPS64 0x0080
#define ISA_MIPS64R20x0100
+#define ISA_MIPS32R3 0x0200
+#define ISA_MIPS32R5 0x0400
/* MIPS ASEs. */
#define ASE_MIPS16 0x1000
@@ -64,6 +66,12 @@
#define CPU_MIPS32R2(CPU_MIPS32 | ISA_MIPS32R2)
#define CPU_MIPS64R2(CPU_MIPS64 | CPU_MIPS32R2 |
ISA_MIPS64R2)
+/* MIPS Technologies Release 3 */
+#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
+
+/* MIPS Technologies Release 5 */
+#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
+
/* Strictly follow the architecture standard:
- Disallow special instruction handling for PMON/SPIM.
Note that we still maintain Count/Compare to match the host clock. */
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c45b1b2..d74a0af 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -333,6 +333,31 @@ static const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
.mmu_type = MMU_TYPE_R4000,
},
+{
+/* A generic CPU providing MIPS32 Release 5 features.
+ FIXME: Eventually this should be replaced by a real CPU model. */
That is not really possible. QEMU needs to keep command line backwards
compatibility, so if you add a generic model now, we will need to live
with the generic model for a long time. What's the difficulty with
taking a real CPU model? Is there no silicon yet or just a code name
rather than a marketing name?
Otherwise the patch looks okay.
Regards,
Andreas
P.S. If you want to ping a patch series, please ping the cover letter.
Sorry it's been taking so long, I'll provide my promised comments on the
KVM series right now...
+.name = mips32r5-generic,
+.CP0_PRid = 0x00019700,
+.CP0_Config0 = MIPS_CONFIG0 | (0x1 CP0C0_AR) |
+(MMU_TYPE_R4000 CP0C0_MT),
+.CP0_Config1 = MIPS_CONFIG1 | (1 CP0C1_FP) | (15 CP0C1_MMU) |
+ (0 CP0C1_IS) | (3 CP0C1_IL) | (1 CP0C1_IA) |
+ (0 CP0C1_DS) | (3 CP0C1_DL) | (1 CP0C1_DA) |
+ (1 CP0C1_CA),
+.CP0_Config2 = MIPS_CONFIG2,
+.CP0_Config3 = MIPS_CONFIG3,
+.CP0_LLAddr_rw_bitmask = 0,
+.CP0_LLAddr_shift = 4,
+.SYNCI_Step = 32,
+.CCRes = 2,
+.CP0_Status_rw_bitmask = 0x3778FF1F,
+.CP1_fcr0 = (1 FCR0_F64) | (1 FCR0_L) | (1 FCR0_W) |
+(1 FCR0_D) | (1 FCR0_S) | (0x93 FCR0_PRID),
+.SEGBITS = 32,
+.PABITS = 32,
+.insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
+.mmu_type = MMU_TYPE_R4000,
+},
#if defined(TARGET_MIPS64)
{
.name = R4000,
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
with the generic model for a long time. What's the difficulty with
taking a real CPU model? Is there no silicon yet
No silicon available yet.
Regards,
Petar
From: Andreas Färber [afaer...@suse.de]
Sent: Monday, February 10, 2014 2:51 PM
To: Petar Jovanovic; qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurel...@aurel32.net
Subject: Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for
MIPS32R5
Am 24.01.2014 17:18, schrieb Petar Jovanovic:
From: Petar Jovanovic petar.jovano...@imgtec.com
Add mips32r5-generic among CPU definitions for MIPS.
Define ISA_MIPS32R3 and ISA_MIPS32R5.
Signed-off-by: Petar Jovanovic petar.jovano...@imgtec.com
---
target-mips/mips-defs.h |8
target-mips/translate_init.c | 25 +
2 files changed, 33 insertions(+)
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index bf094a3..9dfa516 100644
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -29,6 +29,8 @@
#define ISA_MIPS32R20x0040
#define ISA_MIPS64 0x0080
#define ISA_MIPS64R20x0100
+#define ISA_MIPS32R3 0x0200
+#define ISA_MIPS32R5 0x0400
/* MIPS ASEs. */
#define ASE_MIPS16 0x1000
@@ -64,6 +66,12 @@
#define CPU_MIPS32R2(CPU_MIPS32 | ISA_MIPS32R2)
#define CPU_MIPS64R2(CPU_MIPS64 | CPU_MIPS32R2 |
ISA_MIPS64R2)
+/* MIPS Technologies Release 3 */
+#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
+
+/* MIPS Technologies Release 5 */
+#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
+
/* Strictly follow the architecture standard:
- Disallow special instruction handling for PMON/SPIM.
Note that we still maintain Count/Compare to match the host clock. */
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c45b1b2..d74a0af 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -333,6 +333,31 @@ static const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
.mmu_type = MMU_TYPE_R4000,
},
+{
+/* A generic CPU providing MIPS32 Release 5 features.
+ FIXME: Eventually this should be replaced by a real CPU model. */
That is not really possible. QEMU needs to keep command line backwards
compatibility, so if you add a generic model now, we will need to live
with the generic model for a long time. What's the difficulty with
taking a real CPU model? Is there no silicon yet or just a code name
rather than a marketing name?
Otherwise the patch looks okay.
Regards,
Andreas
P.S. If you want to ping a patch series, please ping the cover letter.
Sorry it's been taking so long, I'll provide my promised comments on the
KVM series right now...
+.name = mips32r5-generic,
+.CP0_PRid = 0x00019700,
+.CP0_Config0 = MIPS_CONFIG0 | (0x1 CP0C0_AR) |
+(MMU_TYPE_R4000 CP0C0_MT),
+.CP0_Config1 = MIPS_CONFIG1 | (1 CP0C1_FP) | (15 CP0C1_MMU) |
+ (0 CP0C1_IS) | (3 CP0C1_IL) | (1 CP0C1_IA) |
+ (0 CP0C1_DS) | (3 CP0C1_DL) | (1 CP0C1_DA) |
+ (1 CP0C1_CA),
+.CP0_Config2 = MIPS_CONFIG2,
+.CP0_Config3 = MIPS_CONFIG3,
+.CP0_LLAddr_rw_bitmask = 0,
+.CP0_LLAddr_shift = 4,
+.SYNCI_Step = 32,
+.CCRes = 2,
+.CP0_Status_rw_bitmask = 0x3778FF1F,
+.CP1_fcr0 = (1 FCR0_F64) | (1 FCR0_L) | (1 FCR0_W) |
+(1 FCR0_D) | (1 FCR0_S) | (0x93 FCR0_PRID),
+.SEGBITS = 32,
+.PABITS = 32,
+.insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
+.mmu_type = MMU_TYPE_R4000,
+},
#if defined(TARGET_MIPS64)
{
.name = R4000,
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
On 10 February 2014 13:51, Andreas Färber afaer...@suse.de wrote:
Am 24.01.2014 17:18, schrieb Petar Jovanovic:
From: Petar Jovanovic petar.jovano...@imgtec.com
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -333,6 +333,31 @@ static const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
.mmu_type = MMU_TYPE_R4000,
},
+{
+/* A generic CPU providing MIPS32 Release 5 features.
+ FIXME: Eventually this should be replaced by a real CPU model. */
That is not really possible. QEMU needs to keep command line backwards
compatibility, so if you add a generic model now, we will need to live
with the generic model for a long time. What's the difficulty with
taking a real CPU model? Is there no silicon yet or just a code name
rather than a marketing name?
Good point, though I notice we have two MIPS CPUs already
with this same 'FIXME' comment about being generic.
thanks
-- PMM
Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
Reviewed-by: Eric Johnson eric.john...@imgtec.com
From: qemu-devel-bounces+eric.johnson=imgtec@nongnu.org
[qemu-devel-bounces+eric.johnson=imgtec@nongnu.org] on behalf of Petar
Jovanovic [petar.jovano...@rt-rk.com]
Sent: Friday, January 24, 2014 8:18 AM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurel...@aurel32.net
Subject: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for
MIPS32R5
From: Petar Jovanovic petar.jovano...@imgtec.com
Add mips32r5-generic among CPU definitions for MIPS.
Define ISA_MIPS32R3 and ISA_MIPS32R5.
Signed-off-by: Petar Jovanovic petar.jovano...@imgtec.com
---
target-mips/mips-defs.h |8
target-mips/translate_init.c | 25 +
2 files changed, 33 insertions(+)
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index bf094a3..9dfa516 100644
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -29,6 +29,8 @@
#defineISA_MIPS32R20x0040
#defineISA_MIPS64 0x0080
#defineISA_MIPS64R20x0100
+#define ISA_MIPS32R3 0x0200
+#define ISA_MIPS32R5 0x0400
/* MIPS ASEs. */
#defineASE_MIPS16 0x1000
@@ -64,6 +66,12 @@
#defineCPU_MIPS32R2(CPU_MIPS32 | ISA_MIPS32R2)
#defineCPU_MIPS64R2(CPU_MIPS64 | CPU_MIPS32R2 |
ISA_MIPS64R2)
+/* MIPS Technologies Release 3 */
+#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
+
+/* MIPS Technologies Release 5 */
+#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
+
/* Strictly follow the architecture standard:
- Disallow special instruction handling for PMON/SPIM.
Note that we still maintain Count/Compare to match the host clock. */
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c45b1b2..d74a0af 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -333,6 +333,31 @@ static const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
.mmu_type = MMU_TYPE_R4000,
},
+{
+/* A generic CPU providing MIPS32 Release 5 features.
+ FIXME: Eventually this should be replaced by a real CPU model. */
+.name = mips32r5-generic,
+.CP0_PRid = 0x00019700,
+.CP0_Config0 = MIPS_CONFIG0 | (0x1 CP0C0_AR) |
+(MMU_TYPE_R4000 CP0C0_MT),
+.CP0_Config1 = MIPS_CONFIG1 | (1 CP0C1_FP) | (15 CP0C1_MMU) |
+ (0 CP0C1_IS) | (3 CP0C1_IL) | (1 CP0C1_IA) |
+ (0 CP0C1_DS) | (3 CP0C1_DL) | (1 CP0C1_DA) |
+ (1 CP0C1_CA),
+.CP0_Config2 = MIPS_CONFIG2,
+.CP0_Config3 = MIPS_CONFIG3,
+.CP0_LLAddr_rw_bitmask = 0,
+.CP0_LLAddr_shift = 4,
+.SYNCI_Step = 32,
+.CCRes = 2,
+.CP0_Status_rw_bitmask = 0x3778FF1F,
+.CP1_fcr0 = (1 FCR0_F64) | (1 FCR0_L) | (1 FCR0_W) |
+(1 FCR0_D) | (1 FCR0_S) | (0x93 FCR0_PRID),
+.SEGBITS = 32,
+.PABITS = 32,
+.insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
+.mmu_type = MMU_TYPE_R4000,
+},
#if defined(TARGET_MIPS64)
{
.name = R4000,
--
1.7.9.5
Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
ping
http://patchwork.ozlabs.org/patch/313937/
http://patchwork.ozlabs.org/patch/313938/
http://patchwork.ozlabs.org/patch/313944/
http://patchwork.ozlabs.org/patch/313936/
Regards,
Petar
From: Petar Jovanovic [petar.jovano...@rt-rk.com]
Sent: Friday, January 24, 2014 5:18 PM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurel...@aurel32.net
Subject: [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
From: Petar Jovanovic petar.jovano...@imgtec.com
Add mips32r5-generic among CPU definitions for MIPS.
Define ISA_MIPS32R3 and ISA_MIPS32R5.
Signed-off-by: Petar Jovanovic petar.jovano...@imgtec.com
---
target-mips/mips-defs.h |8
target-mips/translate_init.c | 25 +
2 files changed, 33 insertions(+)
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index bf094a3..9dfa516 100644
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -29,6 +29,8 @@
#defineISA_MIPS32R20x0040
#defineISA_MIPS64 0x0080
#defineISA_MIPS64R20x0100
+#define ISA_MIPS32R3 0x0200
+#define ISA_MIPS32R5 0x0400
/* MIPS ASEs. */
#defineASE_MIPS16 0x1000
@@ -64,6 +66,12 @@
#defineCPU_MIPS32R2(CPU_MIPS32 | ISA_MIPS32R2)
#defineCPU_MIPS64R2(CPU_MIPS64 | CPU_MIPS32R2 |
ISA_MIPS64R2)
+/* MIPS Technologies Release 3 */
+#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
+
+/* MIPS Technologies Release 5 */
+#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
+
/* Strictly follow the architecture standard:
- Disallow special instruction handling for PMON/SPIM.
Note that we still maintain Count/Compare to match the host clock. */
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c45b1b2..d74a0af 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -333,6 +333,31 @@ static const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
.mmu_type = MMU_TYPE_R4000,
},
+{
+/* A generic CPU providing MIPS32 Release 5 features.
+ FIXME: Eventually this should be replaced by a real CPU model. */
+.name = mips32r5-generic,
+.CP0_PRid = 0x00019700,
+.CP0_Config0 = MIPS_CONFIG0 | (0x1 CP0C0_AR) |
+(MMU_TYPE_R4000 CP0C0_MT),
+.CP0_Config1 = MIPS_CONFIG1 | (1 CP0C1_FP) | (15 CP0C1_MMU) |
+ (0 CP0C1_IS) | (3 CP0C1_IL) | (1 CP0C1_IA) |
+ (0 CP0C1_DS) | (3 CP0C1_DL) | (1 CP0C1_DA) |
+ (1 CP0C1_CA),
+.CP0_Config2 = MIPS_CONFIG2,
+.CP0_Config3 = MIPS_CONFIG3,
+.CP0_LLAddr_rw_bitmask = 0,
+.CP0_LLAddr_shift = 4,
+.SYNCI_Step = 32,
+.CCRes = 2,
+.CP0_Status_rw_bitmask = 0x3778FF1F,
+.CP1_fcr0 = (1 FCR0_F64) | (1 FCR0_L) | (1 FCR0_W) |
+(1 FCR0_D) | (1 FCR0_S) | (0x93 FCR0_PRID),
+.SEGBITS = 32,
+.PABITS = 32,
+.insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
+.mmu_type = MMU_TYPE_R4000,
+},
#if defined(TARGET_MIPS64)
{
.name = R4000,
--
1.7.9.5
Re: [Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
ping
http://patchwork.ozlabs.org/patch/313937/
http://patchwork.ozlabs.org/patch/313938/
http://patchwork.ozlabs.org/patch/313944/
http://patchwork.ozlabs.org/patch/313936/
Regards,
Petar
From: Petar Jovanovic [petar.jovano...@rt-rk.com]
Sent: Friday, January 24, 2014 5:18 PM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; aurel...@aurel32.net
Subject: [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
From: Petar Jovanovic petar.jovano...@imgtec.com
Add mips32r5-generic among CPU definitions for MIPS.
Define ISA_MIPS32R3 and ISA_MIPS32R5.
Signed-off-by: Petar Jovanovic petar.jovano...@imgtec.com
---
target-mips/mips-defs.h |8
target-mips/translate_init.c | 25 +
2 files changed, 33 insertions(+)
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index bf094a3..9dfa516 100644
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -29,6 +29,8 @@
#defineISA_MIPS32R20x0040
#defineISA_MIPS64 0x0080
#defineISA_MIPS64R20x0100
+#define ISA_MIPS32R3 0x0200
+#define ISA_MIPS32R5 0x0400
/* MIPS ASEs. */
#defineASE_MIPS16 0x1000
@@ -64,6 +66,12 @@
#defineCPU_MIPS32R2(CPU_MIPS32 | ISA_MIPS32R2)
#defineCPU_MIPS64R2(CPU_MIPS64 | CPU_MIPS32R2 |
ISA_MIPS64R2)
+/* MIPS Technologies Release 3 */
+#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
+
+/* MIPS Technologies Release 5 */
+#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
+
/* Strictly follow the architecture standard:
- Disallow special instruction handling for PMON/SPIM.
Note that we still maintain Count/Compare to match the host clock. */
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c45b1b2..d74a0af 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -333,6 +333,31 @@ static const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
.mmu_type = MMU_TYPE_R4000,
},
+{
+/* A generic CPU providing MIPS32 Release 5 features.
+ FIXME: Eventually this should be replaced by a real CPU model. */
+.name = mips32r5-generic,
+.CP0_PRid = 0x00019700,
+.CP0_Config0 = MIPS_CONFIG0 | (0x1 CP0C0_AR) |
+(MMU_TYPE_R4000 CP0C0_MT),
+.CP0_Config1 = MIPS_CONFIG1 | (1 CP0C1_FP) | (15 CP0C1_MMU) |
+ (0 CP0C1_IS) | (3 CP0C1_IL) | (1 CP0C1_IA) |
+ (0 CP0C1_DS) | (3 CP0C1_DL) | (1 CP0C1_DA) |
+ (1 CP0C1_CA),
+.CP0_Config2 = MIPS_CONFIG2,
+.CP0_Config3 = MIPS_CONFIG3,
+.CP0_LLAddr_rw_bitmask = 0,
+.CP0_LLAddr_shift = 4,
+.SYNCI_Step = 32,
+.CCRes = 2,
+.CP0_Status_rw_bitmask = 0x3778FF1F,
+.CP1_fcr0 = (1 FCR0_F64) | (1 FCR0_L) | (1 FCR0_W) |
+(1 FCR0_D) | (1 FCR0_S) | (0x93 FCR0_PRID),
+.SEGBITS = 32,
+.PABITS = 32,
+.insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
+.mmu_type = MMU_TYPE_R4000,
+},
#if defined(TARGET_MIPS64)
{
.name = R4000,
--
1.7.9.5
[Qemu-devel] [PATCH v2 1/4] target-mips: add CPU definition for MIPS32R5
From: Petar Jovanovic petar.jovano...@imgtec.com
Add mips32r5-generic among CPU definitions for MIPS.
Define ISA_MIPS32R3 and ISA_MIPS32R5.
Signed-off-by: Petar Jovanovic petar.jovano...@imgtec.com
---
target-mips/mips-defs.h |8
target-mips/translate_init.c | 25 +
2 files changed, 33 insertions(+)
diff --git a/target-mips/mips-defs.h b/target-mips/mips-defs.h
index bf094a3..9dfa516 100644
--- a/target-mips/mips-defs.h
+++ b/target-mips/mips-defs.h
@@ -29,6 +29,8 @@
#defineISA_MIPS32R20x0040
#defineISA_MIPS64 0x0080
#defineISA_MIPS64R20x0100
+#define ISA_MIPS32R3 0x0200
+#define ISA_MIPS32R5 0x0400
/* MIPS ASEs. */
#defineASE_MIPS16 0x1000
@@ -64,6 +66,12 @@
#defineCPU_MIPS32R2(CPU_MIPS32 | ISA_MIPS32R2)
#defineCPU_MIPS64R2(CPU_MIPS64 | CPU_MIPS32R2 |
ISA_MIPS64R2)
+/* MIPS Technologies Release 3 */
+#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3)
+
+/* MIPS Technologies Release 5 */
+#define CPU_MIPS32R5 (CPU_MIPS32R3 | ISA_MIPS32R5)
+
/* Strictly follow the architecture standard:
- Disallow special instruction handling for PMON/SPIM.
Note that we still maintain Count/Compare to match the host clock. */
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c45b1b2..d74a0af 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -333,6 +333,31 @@ static const mips_def_t mips_defs[] =
.insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
.mmu_type = MMU_TYPE_R4000,
},
+{
+/* A generic CPU providing MIPS32 Release 5 features.
+ FIXME: Eventually this should be replaced by a real CPU model. */
+.name = mips32r5-generic,
+.CP0_PRid = 0x00019700,
+.CP0_Config0 = MIPS_CONFIG0 | (0x1 CP0C0_AR) |
+(MMU_TYPE_R4000 CP0C0_MT),
+.CP0_Config1 = MIPS_CONFIG1 | (1 CP0C1_FP) | (15 CP0C1_MMU) |
+ (0 CP0C1_IS) | (3 CP0C1_IL) | (1 CP0C1_IA) |
+ (0 CP0C1_DS) | (3 CP0C1_DL) | (1 CP0C1_DA) |
+ (1 CP0C1_CA),
+.CP0_Config2 = MIPS_CONFIG2,
+.CP0_Config3 = MIPS_CONFIG3,
+.CP0_LLAddr_rw_bitmask = 0,
+.CP0_LLAddr_shift = 4,
+.SYNCI_Step = 32,
+.CCRes = 2,
+.CP0_Status_rw_bitmask = 0x3778FF1F,
+.CP1_fcr0 = (1 FCR0_F64) | (1 FCR0_L) | (1 FCR0_W) |
+(1 FCR0_D) | (1 FCR0_S) | (0x93 FCR0_PRID),
+.SEGBITS = 32,
+.PABITS = 32,
+.insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
+.mmu_type = MMU_TYPE_R4000,
+},
#if defined(TARGET_MIPS64)
{
.name = R4000,
--
1.7.9.5
