Re: [Qemu-devel] [PATCH v2 16/17] RISC-V: add vector extension mask instructions

2019-09-12 Thread Richard Henderson 
On 9/11/19 2:25 AM, liuzhiwei wrote:
> +for (i = 0; i < vlmax; i++) {
> +if (i < env->vfp.vstart) {
> +continue;
> +} else if (i < vl) {
> +tmp = ~vector_mask_reg(env, rs1, width, lmul, i) &
> +vector_mask_reg(env, rs2, width, lmul, i);
> +vector_mask_result(env, rd, width, lmul, i, tmp);
> +} else {
> +vector_mask_result(env, rd, width, lmul, i, 0);
> +}
> +}

These can be processed in uint64_t units, with a mask based on width:

   8: 0x
  16: 0x
  32: 0x
  64: 0x0101010101010101

  dest = ~in1 & in2 & mask;

with an additional final mask to handle vl not being a multiple of 64.

Again, I urge you not to bother with impossible vstart -- instructions like
this cannot be interrupted, and the spec allows you to not handle values of
vstart that cannot be produced by the implementation.


r~

[Qemu-devel] [PATCH v2 16/17] RISC-V: add vector extension mask instructions

2019-09-10 Thread liuzhiwei 
From: LIU Zhiwei 

Signed-off-by: LIU Zhiwei 
---
 target/riscv/helper.h   |  16 +
 target/riscv/insn32.decode  |  17 +
 target/riscv/insn_trans/trans_rvv.inc.c |  27 ++
 target/riscv/vector_helper.c| 635 
 4 files changed, 695 insertions(+)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index d36bd00..337ac2e 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -401,5 +401,21 @@ DEF_HELPER_5(vector_vwredsum_vs, void, env, i32, i32, i32, 
i32)
 DEF_HELPER_5(vector_vfwredsum_vs, void, env, i32, i32, i32, i32)
 DEF_HELPER_5(vector_vfwredosum_vs, void, env, i32, i32, i32, i32)
 
+DEF_HELPER_4(vector_vmandnot_mm, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmand_mm, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmor_mm, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmxor_mm, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmornot_mm, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmnand_mm, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmnor_mm, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmxnor_mm, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmsbf_m, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmsof_m, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmsif_m, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_viota_m, void, env, i32, i32, i32)
+DEF_HELPER_3(vector_vid_v, void, env, i32, i32)
+DEF_HELPER_4(vector_vmpopc_m, void, env, i32, i32, i32)
+DEF_HELPER_4(vector_vmfirst_m, void, env, i32, i32, i32)
+
 DEF_HELPER_4(vector_vsetvli, void, env, i32, i32, i32)
 DEF_HELPER_4(vector_vsetvl, void, env, i32, i32, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 3f63bc1..1de776b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -68,6 +68,7 @@
 @r_nfvm  nf:3 ... vm:1 . . ... . ... %rs2 %rs1 %rd
 @r2_nfvm nf:3 ... vm:1 . . ... . ... %rs1 %rd
 @r2_vm   .. vm:1 . . ... . ... %rs2 %rd
+@r1_vm   .. vm:1 . . ... . ... %rd
 @r2_zimm . zimm:11  . ... . ... %rs1 %rd
 
 @sfence_vma ... . .   ... . ... %rs2 %rs1
@@ -541,5 +542,21 @@ vfredmax_vs 000111 . . . 001 . 1010111 
@r_vm
 vfwredsum_vs110001 . . . 001 . 1010111 @r_vm
 vfwredosum_vs   110011 . . . 001 . 1010111 @r_vm
 
+vmand_mm011001 - . . 010 . 1010111 @r
+vmnand_mm   011101 - . . 010 . 1010111 @r
+vmandnot_mm 011000 - . . 010 . 1010111 @r
+vmor_mm 011010 - . . 010 . 1010111 @r
+vmxor_mm011011 - . . 010 . 1010111 @r
+vmnor_mm00 - . . 010 . 1010111 @r
+vmornot_mm  011100 - . . 010 . 1010111 @r
+vmxnor_mm   01 - . . 010 . 1010111 @r
+vmpopc_m010100 . . - 010 . 1010111 @r2_vm
+vmfirst_m   010101 . . - 010 . 1010111 @r2_vm
+vmsbf_m 010110 . . 1 010 . 1010111 @r2_vm
+vmsof_m 010110 . . 00010 010 . 1010111 @r2_vm
+vmsif_m 010110 . . 00011 010 . 1010111 @r2_vm
+viota_m 010110 . . 1 010 . 1010111 @r2_vm
+vid_v   010110 . 0 10001 010 . 1010111 @r1_vm
+
 vsetvli 0 ... . 111 . 1010111  @r2_zimm
 vsetvl  100 . . 111 . 1010111  @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c 
b/target/riscv/insn_trans/trans_rvv.inc.c
index 9a3d31b..85e435a 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -77,6 +77,17 @@ static bool trans_##INSN(DisasContext *ctx, arg_##INSN * a) \
 return true;   \
 }
 
+#define GEN_VECTOR_R1_VM(INSN) \
+static bool trans_##INSN(DisasContext *ctx, arg_##INSN * a) \
+{  \
+TCGv_i32 d  = tcg_const_i32(a->rd);\
+TCGv_i32 vm = tcg_const_i32(a->vm);\
+gen_helper_vector_##INSN(cpu_env, vm, d);\
+tcg_temp_free_i32(d);  \
+tcg_temp_free_i32(vm); \
+return true;   \
+}
+
 #define GEN_VECTOR_R_VM(INSN) \
 static bool trans_##INSN(DisasContext *ctx, arg_##INSN * a) \
 {  \
@@ -444,5 +455,21 @@ GEN_VECTOR_R_VM(vfredmax_vs)
 GEN_VECTOR_R_VM(vfwredsum_vs)
 GEN_VECTOR_R_VM(vfwredosum_vs)
 
+GEN_VECTOR_R(vmandnot_mm)
+GEN_VECTOR_R(vmand_mm)
+GEN_VECTOR_R(vmor_mm)
+GEN_VECTOR_R(vmxor_mm)
+GEN_VECTOR_R(vmornot_mm)
+GEN_VECTOR_R(vmnand_mm)
+GEN_VECTOR_R(vmnor_mm)
+GEN_VECTOR_R(vmxnor_mm)
+GEN_VECTOR_R2_VM(vmpopc_m)
+GEN_VECTOR_R2_VM(vmfirst_m)
+GEN_VECTOR_R2_VM(vmsbf_m)
+GEN_VECTOR_R2_VM(vmsof_m)
+GEN_VECTOR_R2_VM(vmsif_m)
+GEN_VECTOR_R2_VM(viota_m)
+GEN_VECTOR_R1_VM(vid_v)
+
 GEN_VECTOR_R2_ZIMM(vsetvli)