Re: [Qemu-devel] [PATCH v3 1/3] xlnx-zynqmp-rtc: Initial commit
On Wed, Jan 17, 2018 at 12:39 PM, Philippe Mathieu-Daudé
wrote:
> On 01/17/2018 02:27 PM, Alistair Francis wrote:
>> Initial commit of the ZynqMP RTC device.
>>
>> Signed-off-by: Alistair Francis
>> ---
>> V2:
>> - Delete unused realise function
>> - Remove DB_PRINT()
>>
>> hw/timer/Makefile.objs | 1 +
>> hw/timer/xlnx-zynqmp-rtc.c | 218
>> +
>> include/hw/timer/xlnx-zynqmp-rtc.h | 84 ++
>
> Please 'git config diff.orderFile scripts/git.orderfile' :)
>
>> 3 files changed, 303 insertions(+)
>> create mode 100644 hw/timer/xlnx-zynqmp-rtc.c
>> create mode 100644 include/hw/timer/xlnx-zynqmp-rtc.h
>>
>> diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
>> index 8c19eac3b6..8b27a4b7ef 100644
>> --- a/hw/timer/Makefile.objs
>> +++ b/hw/timer/Makefile.objs
>> @@ -21,6 +21,7 @@ common-obj-$(CONFIG_IMX) += imx_epit.o
>> common-obj-$(CONFIG_IMX) += imx_gpt.o
>> common-obj-$(CONFIG_LM32) += lm32_timer.o
>> common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o
>> +common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp-rtc.o
>>
>> obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
>> obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o
>> diff --git a/hw/timer/xlnx-zynqmp-rtc.c b/hw/timer/xlnx-zynqmp-rtc.c
>> new file mode 100644
>> index 00..ead40fc42d
>> --- /dev/null
>> +++ b/hw/timer/xlnx-zynqmp-rtc.c
>> @@ -0,0 +1,218 @@
>> +/*
>> + * QEMU model of the Xilinx ZynqMP Real Time Clock (RTC).
>> + *
>> + * Copyright (c) 2017 Xilinx Inc.
>> + *
>> + * Written-by: Alistair Francis
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> copy
>> + * of this software and associated documentation files (the "Software"), to
>> deal
>> + * in the Software without restriction, including without limitation the
>> rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be included
>> in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
>> OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>> + * THE SOFTWARE.
>
> *
> * SPDX-License-Identifier: MIT
What does this mean? Why is it MIT?
Alistair
>
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "hw/sysbus.h"
>> +#include "hw/register.h"
>> +#include "qemu/bitops.h"
>> +#include "qemu/log.h"
>> +#include "hw/timer/xlnx-zynqmp-rtc.h"
>> +
>> +#ifndef XLNX_ZYNQMP_RTC_ERR_DEBUG
>> +#define XLNX_ZYNQMP_RTC_ERR_DEBUG 0
>> +#endif
>> +
>> +static void rtc_int_update_irq(XlnxZynqMPRTC *s)
>> +{
>> +bool pending = s->regs[R_RTC_INT_STATUS] & ~s->regs[R_RTC_INT_MASK];
>> +qemu_set_irq(s->irq_rtc_int, pending);
>> +}
>> +
>> +static void addr_error_int_update_irq(XlnxZynqMPRTC *s)
>> +{
>> +bool pending = s->regs[R_ADDR_ERROR] & ~s->regs[R_ADDR_ERROR_INT_MASK];
>> +qemu_set_irq(s->irq_addr_error_int, pending);
>> +}
>> +
>> +static void rtc_int_status_postw(RegisterInfo *reg, uint64_t val64)
>> +{
>> +XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
>> +rtc_int_update_irq(s);
>> +}
>> +
>> +static uint64_t rtc_int_en_prew(RegisterInfo *reg, uint64_t val64)
>> +{
>> +XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
>> +uint32_t val = val64;
>> +
>> +s->regs[R_RTC_INT_MASK] &= ~val;
>> +rtc_int_update_irq(s);
>> +return 0;
>> +}
>> +
>> +static uint64_t rtc_int_dis_prew(RegisterInfo *reg, uint64_t val64)
>> +{
>> +XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
>> +uint32_t val = val64;
>> +
>> +s->regs[R_RTC_INT_MASK] |= val;
>> +rtc_int_update_irq(s);
>> +return 0;
>> +}
>> +
>> +static void addr_error_postw(RegisterInfo *reg, uint64_t val64)
>> +{
>> +XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
>> +addr_error_int_update_irq(s);
>> +}
>> +
>> +static uint64_t addr_error_int_en_prew(RegisterInfo *reg, uint64_t val64)
>> +{
>> +XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
>> +uint32_t val = val64;
>> +
>> +s->regs[R_ADDR_ERROR_INT_MASK] &= ~val;
>> +addr_error_int_update_irq(s);
>> +return 0;
>> +}
>> +
>> +static uint64_t addr_error_int_dis_prew(RegisterInfo *reg, uint64_t val64)
>> +{
>> +XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
>> +uint32_t val = val64;
>> +
>> +s->regs[R_ADDR_ERROR_INT_MASK] |= val;
>> +addr_error_int_update_irq(s);
>> +
Re: [Qemu-devel] [PATCH v3 1/3] xlnx-zynqmp-rtc: Initial commit
On 01/17/2018 02:27 PM, Alistair Francis wrote:
> Initial commit of the ZynqMP RTC device.
>
> Signed-off-by: Alistair Francis
> ---
> V2:
> - Delete unused realise function
> - Remove DB_PRINT()
>
> hw/timer/Makefile.objs | 1 +
> hw/timer/xlnx-zynqmp-rtc.c | 218
> +
> include/hw/timer/xlnx-zynqmp-rtc.h | 84 ++
Please 'git config diff.orderFile scripts/git.orderfile' :)
> 3 files changed, 303 insertions(+)
> create mode 100644 hw/timer/xlnx-zynqmp-rtc.c
> create mode 100644 include/hw/timer/xlnx-zynqmp-rtc.h
>
> diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
> index 8c19eac3b6..8b27a4b7ef 100644
> --- a/hw/timer/Makefile.objs
> +++ b/hw/timer/Makefile.objs
> @@ -21,6 +21,7 @@ common-obj-$(CONFIG_IMX) += imx_epit.o
> common-obj-$(CONFIG_IMX) += imx_gpt.o
> common-obj-$(CONFIG_LM32) += lm32_timer.o
> common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o
> +common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp-rtc.o
>
> obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
> obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o
> diff --git a/hw/timer/xlnx-zynqmp-rtc.c b/hw/timer/xlnx-zynqmp-rtc.c
> new file mode 100644
> index 00..ead40fc42d
> --- /dev/null
> +++ b/hw/timer/xlnx-zynqmp-rtc.c
> @@ -0,0 +1,218 @@
> +/*
> + * QEMU model of the Xilinx ZynqMP Real Time Clock (RTC).
> + *
> + * Copyright (c) 2017 Xilinx Inc.
> + *
> + * Written-by: Alistair Francis
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> copy
> + * of this software and associated documentation files (the "Software"), to
> deal
> + * in the Software without restriction, including without limitation the
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
*
* SPDX-License-Identifier: MIT
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/sysbus.h"
> +#include "hw/register.h"
> +#include "qemu/bitops.h"
> +#include "qemu/log.h"
> +#include "hw/timer/xlnx-zynqmp-rtc.h"
> +
> +#ifndef XLNX_ZYNQMP_RTC_ERR_DEBUG
> +#define XLNX_ZYNQMP_RTC_ERR_DEBUG 0
> +#endif
> +
> +static void rtc_int_update_irq(XlnxZynqMPRTC *s)
> +{
> +bool pending = s->regs[R_RTC_INT_STATUS] & ~s->regs[R_RTC_INT_MASK];
> +qemu_set_irq(s->irq_rtc_int, pending);
> +}
> +
> +static void addr_error_int_update_irq(XlnxZynqMPRTC *s)
> +{
> +bool pending = s->regs[R_ADDR_ERROR] & ~s->regs[R_ADDR_ERROR_INT_MASK];
> +qemu_set_irq(s->irq_addr_error_int, pending);
> +}
> +
> +static void rtc_int_status_postw(RegisterInfo *reg, uint64_t val64)
> +{
> +XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
> +rtc_int_update_irq(s);
> +}
> +
> +static uint64_t rtc_int_en_prew(RegisterInfo *reg, uint64_t val64)
> +{
> +XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
> +uint32_t val = val64;
> +
> +s->regs[R_RTC_INT_MASK] &= ~val;
> +rtc_int_update_irq(s);
> +return 0;
> +}
> +
> +static uint64_t rtc_int_dis_prew(RegisterInfo *reg, uint64_t val64)
> +{
> +XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
> +uint32_t val = val64;
> +
> +s->regs[R_RTC_INT_MASK] |= val;
> +rtc_int_update_irq(s);
> +return 0;
> +}
> +
> +static void addr_error_postw(RegisterInfo *reg, uint64_t val64)
> +{
> +XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
> +addr_error_int_update_irq(s);
> +}
> +
> +static uint64_t addr_error_int_en_prew(RegisterInfo *reg, uint64_t val64)
> +{
> +XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
> +uint32_t val = val64;
> +
> +s->regs[R_ADDR_ERROR_INT_MASK] &= ~val;
> +addr_error_int_update_irq(s);
> +return 0;
> +}
> +
> +static uint64_t addr_error_int_dis_prew(RegisterInfo *reg, uint64_t val64)
> +{
> +XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
> +uint32_t val = val64;
> +
> +s->regs[R_ADDR_ERROR_INT_MASK] |= val;
> +addr_error_int_update_irq(s);
> +return 0;
> +}
> +
> +static const RegisterAccessInfo rtc_regs_info[] = {
> +{ .name = "SET_TIME_WRITE", .addr = A_SET_TIME_WRITE,
> +},{ .name = "SET_TIME_READ", .addr = A_SET_TIME_READ,
> +.ro = 0x,
> +},{ .name = "CALIB_WRITE", .ad
[Qemu-devel] [PATCH v3 1/3] xlnx-zynqmp-rtc: Initial commit
Initial commit of the ZynqMP RTC device.
Signed-off-by: Alistair Francis
---
V2:
- Delete unused realise function
- Remove DB_PRINT()
hw/timer/Makefile.objs | 1 +
hw/timer/xlnx-zynqmp-rtc.c | 218 +
include/hw/timer/xlnx-zynqmp-rtc.h | 84 ++
3 files changed, 303 insertions(+)
create mode 100644 hw/timer/xlnx-zynqmp-rtc.c
create mode 100644 include/hw/timer/xlnx-zynqmp-rtc.h
diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index 8c19eac3b6..8b27a4b7ef 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -21,6 +21,7 @@ common-obj-$(CONFIG_IMX) += imx_epit.o
common-obj-$(CONFIG_IMX) += imx_gpt.o
common-obj-$(CONFIG_LM32) += lm32_timer.o
common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o
+common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp-rtc.o
obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o
diff --git a/hw/timer/xlnx-zynqmp-rtc.c b/hw/timer/xlnx-zynqmp-rtc.c
new file mode 100644
index 00..ead40fc42d
--- /dev/null
+++ b/hw/timer/xlnx-zynqmp-rtc.c
@@ -0,0 +1,218 @@
+/*
+ * QEMU model of the Xilinx ZynqMP Real Time Clock (RTC).
+ *
+ * Copyright (c) 2017 Xilinx Inc.
+ *
+ * Written-by: Alistair Francis
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to
deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sysbus.h"
+#include "hw/register.h"
+#include "qemu/bitops.h"
+#include "qemu/log.h"
+#include "hw/timer/xlnx-zynqmp-rtc.h"
+
+#ifndef XLNX_ZYNQMP_RTC_ERR_DEBUG
+#define XLNX_ZYNQMP_RTC_ERR_DEBUG 0
+#endif
+
+static void rtc_int_update_irq(XlnxZynqMPRTC *s)
+{
+bool pending = s->regs[R_RTC_INT_STATUS] & ~s->regs[R_RTC_INT_MASK];
+qemu_set_irq(s->irq_rtc_int, pending);
+}
+
+static void addr_error_int_update_irq(XlnxZynqMPRTC *s)
+{
+bool pending = s->regs[R_ADDR_ERROR] & ~s->regs[R_ADDR_ERROR_INT_MASK];
+qemu_set_irq(s->irq_addr_error_int, pending);
+}
+
+static void rtc_int_status_postw(RegisterInfo *reg, uint64_t val64)
+{
+XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
+rtc_int_update_irq(s);
+}
+
+static uint64_t rtc_int_en_prew(RegisterInfo *reg, uint64_t val64)
+{
+XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
+uint32_t val = val64;
+
+s->regs[R_RTC_INT_MASK] &= ~val;
+rtc_int_update_irq(s);
+return 0;
+}
+
+static uint64_t rtc_int_dis_prew(RegisterInfo *reg, uint64_t val64)
+{
+XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
+uint32_t val = val64;
+
+s->regs[R_RTC_INT_MASK] |= val;
+rtc_int_update_irq(s);
+return 0;
+}
+
+static void addr_error_postw(RegisterInfo *reg, uint64_t val64)
+{
+XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
+addr_error_int_update_irq(s);
+}
+
+static uint64_t addr_error_int_en_prew(RegisterInfo *reg, uint64_t val64)
+{
+XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
+uint32_t val = val64;
+
+s->regs[R_ADDR_ERROR_INT_MASK] &= ~val;
+addr_error_int_update_irq(s);
+return 0;
+}
+
+static uint64_t addr_error_int_dis_prew(RegisterInfo *reg, uint64_t val64)
+{
+XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
+uint32_t val = val64;
+
+s->regs[R_ADDR_ERROR_INT_MASK] |= val;
+addr_error_int_update_irq(s);
+return 0;
+}
+
+static const RegisterAccessInfo rtc_regs_info[] = {
+{ .name = "SET_TIME_WRITE", .addr = A_SET_TIME_WRITE,
+},{ .name = "SET_TIME_READ", .addr = A_SET_TIME_READ,
+.ro = 0x,
+},{ .name = "CALIB_WRITE", .addr = A_CALIB_WRITE,
+},{ .name = "CALIB_READ", .addr = A_CALIB_READ,
+.ro = 0x1f,
+},{ .name = "CURRENT_TIME", .addr = A_CURRENT_TIME,
+.ro = 0x,
+},{ .name = "CURRENT_TICK", .addr = A_CURRENT_TICK,
+.ro = 0x,
+},{ .name = "ALARM", .addr = A_ALARM,
+},{ .name = "RTC_INT_STATUS", .addr = A_RTC_INT_STATUS,
+.w1c = 0x3,
+.post_write = rtc_int_status_postw,
+},
