Re: [Qemu-devel] [PATCH v3 1/7] MIPS: Initial support of bonito north bridge used by fulong mini pc
On Fri, Jun 04, 2010 at 04:37:43PM +0800, Huacai Chen wrote: > Signed-off-by: Huacai Chen > --- > Makefile.target |1 + > default-configs/mips64el-softmmu.mak |1 + > hw/bonito.c | 816 > ++ > hw/mips.h|3 + > 4 files changed, 821 insertions(+), 0 deletions(-) > create mode 100644 hw/bonito.c > > diff --git a/Makefile.target b/Makefile.target > index d06c679..ac36e2c 100644 > --- a/Makefile.target > +++ b/Makefile.target > @@ -221,6 +221,7 @@ obj-mips-y += vga.o i8259.o > obj-mips-y += g364fb.o jazz_led.o > obj-mips-y += gt64xxx.o mc146818rtc.o > obj-mips-y += piix4.o cirrus_vga.o > +obj-mips-$(CONFIG_FULONG) += bonito.o > > obj-microblaze-y = petalogix_s3adsp1800_mmu.o > > diff --git a/default-configs/mips64el-softmmu.mak > b/default-configs/mips64el-softmmu.mak > index b372c1d..d35d923 100644 > --- a/default-configs/mips64el-softmmu.mak > +++ b/default-configs/mips64el-softmmu.mak > @@ -29,3 +29,4 @@ CONFIG_DP8393X=y > CONFIG_DS1225Y=y > CONFIG_MIPSNET=y > CONFIG_PFLASH_CFI01=y > +CONFIG_FULONG=y > diff --git a/hw/bonito.c b/hw/bonito.c > new file mode 100644 > index 000..4f21042 > --- /dev/null > +++ b/hw/bonito.c > @@ -0,0 +1,816 @@ > +/* > + * bonito north bridge support > + * > + * Copyright (c) 2008 yajin (ya...@vm-kernel.org) > + * Copyright (c) 2010 Huacai Chen (zltjiang...@gmail.com) > + * > + * This code is licensed under the GNU GPL v2. > + */ > + > +/* > + * fulong 2e mini pc has a bonito north bridge. > + */ > + > +/* what is the meaning of devfn in qemu and IDSEL in bonito northbridge? > + * > + * devfn pci_slot<<3 + funno > + * one pci bus can have 32 devices and each device can have 8 functions. > + * > + * In bonito north bridge, pci slot = IDSEL bit - 12. > + * For example, PCI_IDSEL_VIA686B = 17, > + * pci slot = 17-12=5 > + * > + * so > + * VT686B_FUN0's devfn = (5<<3)+0 > + * VT686B_FUN1's devfn = (5<<3)+1 > + * > + * qemu also uses pci address for north bridge to access pci config register. > + * bus_no [23:16] > + * dev_no [15:11] > + * fun_no [10:8] > + * reg_no [7:2] > + * > + * so function bonito_sbridge_pciaddr for the translation from > + * north bridge address to pci address. > + */ > + > +#include > + > +#include "hw.h" > +#include "pci.h" > +#include "pc.h" > +#include "mips.h" > +#include "pci_host.h" > + > +//#define DEBUG_BONITO > + > +#ifdef DEBUG_BONITO > +#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, > ##__VA_ARGS__) > +#else > +#define DPRINTF(fmt, ...) > +#endif > + > +/* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/ > +#define BONITO_BOOT_BASE0x1fc0 > +#define BONITO_BOOT_SIZE0x0010 > +#define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1) > +#define BONITO_FLASH_BASE 0x1c00 > +#define BONITO_FLASH_SIZE 0x0300 > +#define BONITO_FLASH_TOP(BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1) > +#define BONITO_SOCKET_BASE 0x1f80 > +#define BONITO_SOCKET_SIZE 0x0040 > +#define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1) > +#define BONITO_REG_BASE 0x1fe0 > +#define BONITO_REG_SIZE 0x0004 > +#define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1) > +#define BONITO_DEV_BASE 0x1ff0 > +#define BONITO_DEV_SIZE 0x0010 > +#define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1) > +#define BONITO_PCILO_BASE 0x1000 > +#define BONITO_PCILO_BASE_VA0xb000 > +#define BONITO_PCILO_SIZE 0x0c00 > +#define BONITO_PCILO_TOP(BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1) > +#define BONITO_PCILO0_BASE 0x1000 > +#define BONITO_PCILO1_BASE 0x1400 > +#define BONITO_PCILO2_BASE 0x1800 > +#define BONITO_PCIHI_BASE 0x2000 > +#define BONITO_PCIHI_SIZE 0x2000 > +#define BONITO_PCIHI_TOP(BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1) > +#define BONITO_PCIIO_BASE 0x1fd0 > +#define BONITO_PCIIO_BASE_VA0xbfd0 > +#define BONITO_PCIIO_SIZE 0x0001 > +#define BONITO_PCIIO_TOP(BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1) > +#define BONITO_PCICFG_BASE 0x1fe8 > +#define BONITO_PCICFG_SIZE 0x0008 > +#define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1) > + > + > +#define BONITO_PCICONFIGBASE0x00 > +#define BONITO_REGBASE 0x100 > + > +#define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE+BONITO_REG_BASE) > +#define BONITO_PCICONFIG_SIZE (0x100) > + > +#define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE+BONITO_REG_BASE) > +#define BONITO_INTERNAL_REG_SIZE (0x70) > + > +#define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE) > +#define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE) > + > + > + > +/* 1. Bonito h/w Configuration */ > +/* Power on register */ > + > +#define BONITO_BONPONCFG(0x00 >> 2) /
[Qemu-devel] [PATCH v3 1/7] MIPS: Initial support of bonito north bridge used by fulong mini pc
Signed-off-by: Huacai Chen --- Makefile.target |1 + default-configs/mips64el-softmmu.mak |1 + hw/bonito.c | 816 ++ hw/mips.h|3 + 4 files changed, 821 insertions(+), 0 deletions(-) create mode 100644 hw/bonito.c diff --git a/Makefile.target b/Makefile.target index d06c679..ac36e2c 100644 --- a/Makefile.target +++ b/Makefile.target @@ -221,6 +221,7 @@ obj-mips-y += vga.o i8259.o obj-mips-y += g364fb.o jazz_led.o obj-mips-y += gt64xxx.o mc146818rtc.o obj-mips-y += piix4.o cirrus_vga.o +obj-mips-$(CONFIG_FULONG) += bonito.o obj-microblaze-y = petalogix_s3adsp1800_mmu.o diff --git a/default-configs/mips64el-softmmu.mak b/default-configs/mips64el-softmmu.mak index b372c1d..d35d923 100644 --- a/default-configs/mips64el-softmmu.mak +++ b/default-configs/mips64el-softmmu.mak @@ -29,3 +29,4 @@ CONFIG_DP8393X=y CONFIG_DS1225Y=y CONFIG_MIPSNET=y CONFIG_PFLASH_CFI01=y +CONFIG_FULONG=y diff --git a/hw/bonito.c b/hw/bonito.c new file mode 100644 index 000..4f21042 --- /dev/null +++ b/hw/bonito.c @@ -0,0 +1,816 @@ +/* + * bonito north bridge support + * + * Copyright (c) 2008 yajin (ya...@vm-kernel.org) + * Copyright (c) 2010 Huacai Chen (zltjiang...@gmail.com) + * + * This code is licensed under the GNU GPL v2. + */ + +/* + * fulong 2e mini pc has a bonito north bridge. + */ + +/* what is the meaning of devfn in qemu and IDSEL in bonito northbridge? + * + * devfn pci_slot<<3 + funno + * one pci bus can have 32 devices and each device can have 8 functions. + * + * In bonito north bridge, pci slot = IDSEL bit - 12. + * For example, PCI_IDSEL_VIA686B = 17, + * pci slot = 17-12=5 + * + * so + * VT686B_FUN0's devfn = (5<<3)+0 + * VT686B_FUN1's devfn = (5<<3)+1 + * + * qemu also uses pci address for north bridge to access pci config register. + * bus_no [23:16] + * dev_no [15:11] + * fun_no [10:8] + * reg_no [7:2] + * + * so function bonito_sbridge_pciaddr for the translation from + * north bridge address to pci address. + */ + +#include + +#include "hw.h" +#include "pci.h" +#include "pc.h" +#include "mips.h" +#include "pci_host.h" + +//#define DEBUG_BONITO + +#ifdef DEBUG_BONITO +#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__) +#else +#define DPRINTF(fmt, ...) +#endif + +/* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/ +#define BONITO_BOOT_BASE0x1fc0 +#define BONITO_BOOT_SIZE0x0010 +#define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1) +#define BONITO_FLASH_BASE 0x1c00 +#define BONITO_FLASH_SIZE 0x0300 +#define BONITO_FLASH_TOP(BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1) +#define BONITO_SOCKET_BASE 0x1f80 +#define BONITO_SOCKET_SIZE 0x0040 +#define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1) +#define BONITO_REG_BASE 0x1fe0 +#define BONITO_REG_SIZE 0x0004 +#define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1) +#define BONITO_DEV_BASE 0x1ff0 +#define BONITO_DEV_SIZE 0x0010 +#define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1) +#define BONITO_PCILO_BASE 0x1000 +#define BONITO_PCILO_BASE_VA0xb000 +#define BONITO_PCILO_SIZE 0x0c00 +#define BONITO_PCILO_TOP(BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1) +#define BONITO_PCILO0_BASE 0x1000 +#define BONITO_PCILO1_BASE 0x1400 +#define BONITO_PCILO2_BASE 0x1800 +#define BONITO_PCIHI_BASE 0x2000 +#define BONITO_PCIHI_SIZE 0x2000 +#define BONITO_PCIHI_TOP(BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1) +#define BONITO_PCIIO_BASE 0x1fd0 +#define BONITO_PCIIO_BASE_VA0xbfd0 +#define BONITO_PCIIO_SIZE 0x0001 +#define BONITO_PCIIO_TOP(BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1) +#define BONITO_PCICFG_BASE 0x1fe8 +#define BONITO_PCICFG_SIZE 0x0008 +#define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1) + + +#define BONITO_PCICONFIGBASE0x00 +#define BONITO_REGBASE 0x100 + +#define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE+BONITO_REG_BASE) +#define BONITO_PCICONFIG_SIZE (0x100) + +#define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE+BONITO_REG_BASE) +#define BONITO_INTERNAL_REG_SIZE (0x70) + +#define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE) +#define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE) + + + +/* 1. Bonito h/w Configuration */ +/* Power on register */ + +#define BONITO_BONPONCFG(0x00 >> 2) /* 0x100 */ +#define BONITO_BONGENCFG_OFFSET 0x4 +#define BONITO_BONGENCFG(BONITO_BONGENCFG_OFFSET>>2) /*0x104 */ + +/* 2. IO & IDE configuration */ +#define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */ + +/* 3. IO & IDE configuration */ +#define BONITO_SDCFG(0x0c >> 2) /* 0x10c */ + +/* 4. PCI address map control
