Re: [Qemu-devel] [PATCH v4 8/9] target/ppc: move FP and VMX registers into aligned vsr register array
On 02/01/2019 06:35, David Gibson wrote: > On Sun, Dec 23, 2018 at 11:15:24AM +, Mark Cave-Ayland wrote: >> The VSX register array is a block of 64 128-bit registers where the first 32 >> registers consist of the existing 64-bit FP registers extended to 128-bit >> using new VSR registers, and the last 32 registers are the VMX 128-bit >> registers as show below: >> >> 64-bit 64-bit >> +++ >> |FP0 || VSR0 >> +++ >> |FP1 || VSR1 >> +++ >> |... |... | ... >> +++ >> |FP30|| VSR30 >> +++ >> |FP31|| VSR31 >> +++ >> | VMX0 | VSR32 >> +-+ >> | VMX1 | VSR33 >> +-+ >> | ...| ... >> +-+ >> | VMX30 | VSR62 >> +-+ >> | VMX31 | VSR63 >> +-+ >> >> In order to allow for future conversion of VSX instructions to use TCG vector >> operations, recreate the same layout using an aligned version of the existing >> vsr register array. >> >> Since the old fpr and avr register arrays are removed, the existing callers >> must also be updated to use the correct offset in the vsr register array. >> This >> also includes switching the relevant VMState fields over to using subarrays >> to make sure that migration is preserved. >> >> Signed-off-by: Mark Cave-Ayland >> Reviewed-by: Richard Henderson >> Acked-by: David Gibson > > Sorry, I had to pull this out of ppc-for-4.0 again (and I pulled all > the later patches in the series out for safety as well). It breaks > build on a ppc host - looks like you haven't updated the code to push > pull the VSX state to KVM. Apologies for that. I've now fixed up and compile tested target/ppc/kvm.c on a PPC host, and will post an updated v5 shortly. ATB, Mark.
Re: [Qemu-devel] [PATCH v4 8/9] target/ppc: move FP and VMX registers into aligned vsr register array
On Sun, Dec 23, 2018 at 11:15:24AM +, Mark Cave-Ayland wrote:
> The VSX register array is a block of 64 128-bit registers where the first 32
> registers consist of the existing 64-bit FP registers extended to 128-bit
> using new VSR registers, and the last 32 registers are the VMX 128-bit
> registers as show below:
>
> 64-bit 64-bit
> +++
> |FP0 || VSR0
> +++
> |FP1 || VSR1
> +++
> |... |... | ...
> +++
> |FP30|| VSR30
> +++
> |FP31|| VSR31
> +++
> | VMX0 | VSR32
> +-+
> | VMX1 | VSR33
> +-+
> | ...| ...
> +-+
> | VMX30 | VSR62
> +-+
> | VMX31 | VSR63
> +-+
>
> In order to allow for future conversion of VSX instructions to use TCG vector
> operations, recreate the same layout using an aligned version of the existing
> vsr register array.
>
> Since the old fpr and avr register arrays are removed, the existing callers
> must also be updated to use the correct offset in the vsr register array. This
> also includes switching the relevant VMState fields over to using subarrays
> to make sure that migration is preserved.
>
> Signed-off-by: Mark Cave-Ayland
> Reviewed-by: Richard Henderson
> Acked-by: David Gibson
Sorry, I had to pull this out of ppc-for-4.0 again (and I pulled all
the later patches in the series out for safety as well). It breaks
build on a ppc host - looks like you haven't updated the code to push
pull the VSX state to KVM.
> ---
> linux-user/ppc/signal.c | 28 ---
> target/ppc/arch_dump.c | 15
> target/ppc/cpu.h| 25 +
> target/ppc/gdbstub.c| 8 ++---
> target/ppc/internal.h | 18 +++---
> target/ppc/machine.c| 72
> ++---
> target/ppc/monitor.c| 4 +--
> target/ppc/translate.c | 14
> target/ppc/translate/dfp-impl.inc.c | 2 +-
> target/ppc/translate/vmx-impl.inc.c | 7 +++-
> target/ppc/translate/vsx-impl.inc.c | 4 +--
> target/ppc/translate_init.inc.c | 26 +++---
> 12 files changed, 151 insertions(+), 72 deletions(-)
>
> diff --git a/linux-user/ppc/signal.c b/linux-user/ppc/signal.c
> index 2ae120a2bc..619a56950d 100644
> --- a/linux-user/ppc/signal.c
> +++ b/linux-user/ppc/signal.c
> @@ -258,8 +258,8 @@ static void save_user_regs(CPUPPCState *env, struct
> target_mcontext *frame)
> /* Save Altivec registers if necessary. */
> if (env->insns_flags & PPC_ALTIVEC) {
> uint32_t *vrsave;
> -for (i = 0; i < ARRAY_SIZE(env->avr); i++) {
> -ppc_avr_t *avr = >avr[i];
> +for (i = 0; i < 32; i++) {
> +ppc_avr_t *avr = cpu_avr_ptr(env, i);
> ppc_avr_t *vreg = (ppc_avr_t *)>mc_vregs.altivec[i];
>
> __put_user(avr->u64[PPC_VEC_HI], >u64[0]);
> @@ -281,15 +281,17 @@ static void save_user_regs(CPUPPCState *env, struct
> target_mcontext *frame)
> /* Save VSX second halves */
> if (env->insns_flags2 & PPC2_VSX) {
> uint64_t *vsregs = (uint64_t *)>mc_vregs.altivec[34];
> -for (i = 0; i < ARRAY_SIZE(env->vsr); i++) {
> -__put_user(env->vsr[i], [i]);
> +for (i = 0; i < 32; i++) {
> +uint64_t *vsrl = cpu_vsrl_ptr(env, i);
> +__put_user(*vsrl, [i]);
> }
> }
>
> /* Save floating point registers. */
> if (env->insns_flags & PPC_FLOAT) {
> -for (i = 0; i < ARRAY_SIZE(env->fpr); i++) {
> -__put_user(env->fpr[i], >mc_fregs[i]);
> +for (i = 0; i < 32; i++) {
> +uint64_t *fpr = cpu_fpr_ptr(env, i);
> +__put_user(*fpr, >mc_fregs[i]);
> }
> __put_user((uint64_t) env->fpscr, >mc_fregs[32]);
> }
> @@ -373,8 +375,8 @@ static void restore_user_regs(CPUPPCState *env,
> #else
> v_regs = (ppc_avr_t *)frame->mc_vregs.altivec;
> #endif
> -for (i = 0; i < ARRAY_SIZE(env->avr); i++) {
> -ppc_avr_t *avr = >avr[i];
> +for (i = 0; i < 32; i++) {
> +ppc_avr_t *avr = cpu_avr_ptr(env, i);
>
[Qemu-devel] [PATCH v4 8/9] target/ppc: move FP and VMX registers into aligned vsr register array
The VSX register array is a block of 64 128-bit registers where the first 32
registers consist of the existing 64-bit FP registers extended to 128-bit
using new VSR registers, and the last 32 registers are the VMX 128-bit
registers as show below:
64-bit 64-bit
+++
|FP0 || VSR0
+++
|FP1 || VSR1
+++
|... |... | ...
+++
|FP30|| VSR30
+++
|FP31|| VSR31
+++
| VMX0 | VSR32
+-+
| VMX1 | VSR33
+-+
| ...| ...
+-+
| VMX30 | VSR62
+-+
| VMX31 | VSR63
+-+
In order to allow for future conversion of VSX instructions to use TCG vector
operations, recreate the same layout using an aligned version of the existing
vsr register array.
Since the old fpr and avr register arrays are removed, the existing callers
must also be updated to use the correct offset in the vsr register array. This
also includes switching the relevant VMState fields over to using subarrays
to make sure that migration is preserved.
Signed-off-by: Mark Cave-Ayland
Reviewed-by: Richard Henderson
Acked-by: David Gibson
---
linux-user/ppc/signal.c | 28 ---
target/ppc/arch_dump.c | 15
target/ppc/cpu.h| 25 +
target/ppc/gdbstub.c| 8 ++---
target/ppc/internal.h | 18 +++---
target/ppc/machine.c| 72 ++---
target/ppc/monitor.c| 4 +--
target/ppc/translate.c | 14
target/ppc/translate/dfp-impl.inc.c | 2 +-
target/ppc/translate/vmx-impl.inc.c | 7 +++-
target/ppc/translate/vsx-impl.inc.c | 4 +--
target/ppc/translate_init.inc.c | 26 +++---
12 files changed, 151 insertions(+), 72 deletions(-)
diff --git a/linux-user/ppc/signal.c b/linux-user/ppc/signal.c
index 2ae120a2bc..619a56950d 100644
--- a/linux-user/ppc/signal.c
+++ b/linux-user/ppc/signal.c
@@ -258,8 +258,8 @@ static void save_user_regs(CPUPPCState *env, struct
target_mcontext *frame)
/* Save Altivec registers if necessary. */
if (env->insns_flags & PPC_ALTIVEC) {
uint32_t *vrsave;
-for (i = 0; i < ARRAY_SIZE(env->avr); i++) {
-ppc_avr_t *avr = >avr[i];
+for (i = 0; i < 32; i++) {
+ppc_avr_t *avr = cpu_avr_ptr(env, i);
ppc_avr_t *vreg = (ppc_avr_t *)>mc_vregs.altivec[i];
__put_user(avr->u64[PPC_VEC_HI], >u64[0]);
@@ -281,15 +281,17 @@ static void save_user_regs(CPUPPCState *env, struct
target_mcontext *frame)
/* Save VSX second halves */
if (env->insns_flags2 & PPC2_VSX) {
uint64_t *vsregs = (uint64_t *)>mc_vregs.altivec[34];
-for (i = 0; i < ARRAY_SIZE(env->vsr); i++) {
-__put_user(env->vsr[i], [i]);
+for (i = 0; i < 32; i++) {
+uint64_t *vsrl = cpu_vsrl_ptr(env, i);
+__put_user(*vsrl, [i]);
}
}
/* Save floating point registers. */
if (env->insns_flags & PPC_FLOAT) {
-for (i = 0; i < ARRAY_SIZE(env->fpr); i++) {
-__put_user(env->fpr[i], >mc_fregs[i]);
+for (i = 0; i < 32; i++) {
+uint64_t *fpr = cpu_fpr_ptr(env, i);
+__put_user(*fpr, >mc_fregs[i]);
}
__put_user((uint64_t) env->fpscr, >mc_fregs[32]);
}
@@ -373,8 +375,8 @@ static void restore_user_regs(CPUPPCState *env,
#else
v_regs = (ppc_avr_t *)frame->mc_vregs.altivec;
#endif
-for (i = 0; i < ARRAY_SIZE(env->avr); i++) {
-ppc_avr_t *avr = >avr[i];
+for (i = 0; i < 32; i++) {
+ppc_avr_t *avr = cpu_avr_ptr(env, i);
ppc_avr_t *vreg = _regs[i];
__get_user(avr->u64[PPC_VEC_HI], >u64[0]);
@@ -393,16 +395,18 @@ static void restore_user_regs(CPUPPCState *env,
/* Restore VSX second halves */
if (env->insns_flags2 & PPC2_VSX) {
uint64_t *vsregs = (uint64_t *)>mc_vregs.altivec[34];
-for (i = 0; i < ARRAY_SIZE(env->vsr); i++) {
-__get_user(env->vsr[i], [i]);
+for (i = 0; i < 32; i++) {
+uint64_t *vsrl = cpu_vsrl_ptr(env, i);
+__get_user(*vsrl,
