Re: [Qemu-devel] [PATCH v5 36/36] ppc/pnv: add XIVE support
On 12/3/18 3:26 AM, David Gibson wrote: > On Fri, Nov 16, 2018 at 11:57:29AM +0100, Cédric Le Goater wrote: >> This is simple model of the POWER9 XIVE interrupt controller for the >> PowerNV machine. XIVE for baremetal is a complex controller and the >> model only addresses the needs of the skiboot firmware. >> >> * Overall architecture >> >> XIVE Interrupt Controller >> +-+ IPIs >> | +-+ +-+ +-+ |++ >> | |VC | |CQ | |PC |> | CORES | >> | | esb | | | | |> || >> | | eas | | Bridge | | |> || >> | |SC end | | | | nvt | ||| >> +--+ | +-+ +++ +-+ |+--+-+-+-+ >> | RAM | +--|--+ | | | >> | | | | | | >> | | | | | | >> | | +-v--v-v-v---+ >> other >> | <---+ Power Bus+> >> chips >> | esb | +---+---++ >> | eas | | | >> | end | | | >> | nvt | +---++ +---++ >> +--+ |SC | |SC | >>|| || >>| 2-bits | | 2-bits | >>| local | | VC | >>++ ++ >> PCIe NX,NPU,CAPI >> >> SC: Source Controller (aka. IVSE) >> VC: Virtualization Controller (aka. IVRE) >> CQ: Common Queue (Bridge) >> PC: Presentation Controller (aka. IVPE) >> >> 2-bits: source state machine >> esb: Event State Buffer (Array of PQ bits in an IVSE) >> eas: Event Assignment Structure >> end: Event Notification Descriptor >> nvt: Notification Virtual Target >> >> It is composed of three sub-engines : >> >> - Interrupt Virtualization Source Engine (IVSE), or Source >> Controller (SC). These are found in PCI PHBs, in the PSI host >> bridge controller, but also inside the main controller for the >> core IPIs and other sub-chips (NX, CAP, NPU) of the >> chip/processor. They are configured to feed the IVRE with events. >> >> - Interrupt Virtualization Routing Engine (IVRE) or Virtualization >> Controller (VC). Its job is to match an event source with an Event >> Notification Descriptor (END). >> >> - Interrupt Virtualization Presentation Engine (IVPE) or Presentation >> Controller (PC). It maintains the interrupt context state of each >> thread and handles the delivery of the external exception to the >> thread. >> >> * XIVE internal tables >> >> Each of the sub-engines uses a set of tables to redirect exceptions >> from event sources to CPU threads. >> >> +---+ >>User or OS| EQ | >>or+-->|entries| >>Hypervisor| | .. | >> Memory | +---+ >> | ^ >> | | >>+--+ >> | | >>Hypervisor+--++---+--++---+--+ +--+ >> Memory | ESB || EAT || ENDT | | NVTT | >> (skiboot)++-+++-+++-+ +--+ >>^ |^ |^ | ^ >>| || || | | >>+--+ >>| || || | | >>| || || | | >> +-|--||--||--|-+ +-|-++--+ >> | | || || | | | | tctx||Thread| >> IPI or + + v+ v+ v |---| + .. |-> | >>HW events | | | || | >> | IVRE| | IVPE |+--+ >> +--+ +---+ >> >> The IVSE have a 2-bits, P for pending and Q for queued, state machine >> for each source that allows events to be triggered. They are stored in >> an array, the Event
Re: [Qemu-devel] [PATCH v5 36/36] ppc/pnv: add XIVE support
On Fri, Nov 16, 2018 at 11:57:29AM +0100, Cédric Le Goater wrote: > This is simple model of the POWER9 XIVE interrupt controller for the > PowerNV machine. XIVE for baremetal is a complex controller and the > model only addresses the needs of the skiboot firmware. > > * Overall architecture > > XIVE Interrupt Controller > +-+ IPIs > | +-+ +-+ +-+ |++ > | |VC | |CQ | |PC |> | CORES | > | | esb | | | | |> || > | | eas | | Bridge | | |> || > | |SC end | | | | nvt | ||| > +--+ | +-+ +++ +-+ |+--+-+-+-+ > | RAM | +--|--+ | | | > | | | | | | > | | | | | | > | | +-v--v-v-v---+ > other > | <---+ Power Bus+> > chips > | esb | +---+---++ > | eas | | | > | end | | | > | nvt | +---++ +---++ > +--+ |SC | |SC | >|| || >| 2-bits | | 2-bits | >| local | | VC | >++ ++ > PCIe NX,NPU,CAPI > > SC: Source Controller (aka. IVSE) > VC: Virtualization Controller (aka. IVRE) > CQ: Common Queue (Bridge) > PC: Presentation Controller (aka. IVPE) > > 2-bits: source state machine > esb: Event State Buffer (Array of PQ bits in an IVSE) > eas: Event Assignment Structure > end: Event Notification Descriptor > nvt: Notification Virtual Target > > It is composed of three sub-engines : > > - Interrupt Virtualization Source Engine (IVSE), or Source > Controller (SC). These are found in PCI PHBs, in the PSI host > bridge controller, but also inside the main controller for the > core IPIs and other sub-chips (NX, CAP, NPU) of the > chip/processor. They are configured to feed the IVRE with events. > > - Interrupt Virtualization Routing Engine (IVRE) or Virtualization > Controller (VC). Its job is to match an event source with an Event > Notification Descriptor (END). > > - Interrupt Virtualization Presentation Engine (IVPE) or Presentation > Controller (PC). It maintains the interrupt context state of each > thread and handles the delivery of the external exception to the > thread. > > * XIVE internal tables > > Each of the sub-engines uses a set of tables to redirect exceptions > from event sources to CPU threads. > > +---+ >User or OS| EQ | >or+-->|entries| >Hypervisor| | .. | > Memory | +---+ > | ^ > | | >+--+ > | | >Hypervisor+--++---+--++---+--+ +--+ > Memory | ESB || EAT || ENDT | | NVTT | > (skiboot)++-+++-+++-+ +--+ >^ |^ |^ | ^ >| || || | | >+--+ >| || || | | >| || || | | > +-|--||--||--|-+ +-|-++--+ > | | || || | | | | tctx||Thread| > IPI or + + v+ v+ v |---| + .. |-> | >HW events | | | || | > | IVRE| | IVPE |+--+ > +--+ +---+ > > The IVSE have a 2-bits, P for pending and Q for queued, state machine > for each source that allows events to be triggered. They are stored in > an array, the Event State Buffer (ESB) and controlled by MMIOs. > > If the event is let through, the IVRE looks up in the Event Assignment >
[Qemu-devel] [PATCH v5 36/36] ppc/pnv: add XIVE support
This is simple model of the POWER9 XIVE interrupt controller for the PowerNV machine. XIVE for baremetal is a complex controller and the model only addresses the needs of the skiboot firmware. * Overall architecture XIVE Interrupt Controller +-+ IPIs | +-+ +-+ +-+ |++ | |VC | |CQ | |PC |> | CORES | | | esb | | | | |> || | | eas | | Bridge | | |> || | |SC end | | | | nvt | ||| +--+ | +-+ +++ +-+ |+--+-+-+-+ | RAM | +--|--+ | | | | | | | | | | | | | | | | | +-v--v-v-v---+ other | <---+ Power Bus+> chips | esb | +---+---++ | eas | | | | end | | | | nvt | +---++ +---++ +--+ |SC | |SC | || || | 2-bits | | 2-bits | | local | | VC | ++ ++ PCIe NX,NPU,CAPI SC: Source Controller (aka. IVSE) VC: Virtualization Controller (aka. IVRE) CQ: Common Queue (Bridge) PC: Presentation Controller (aka. IVPE) 2-bits: source state machine esb: Event State Buffer (Array of PQ bits in an IVSE) eas: Event Assignment Structure end: Event Notification Descriptor nvt: Notification Virtual Target It is composed of three sub-engines : - Interrupt Virtualization Source Engine (IVSE), or Source Controller (SC). These are found in PCI PHBs, in the PSI host bridge controller, but also inside the main controller for the core IPIs and other sub-chips (NX, CAP, NPU) of the chip/processor. They are configured to feed the IVRE with events. - Interrupt Virtualization Routing Engine (IVRE) or Virtualization Controller (VC). Its job is to match an event source with an Event Notification Descriptor (END). - Interrupt Virtualization Presentation Engine (IVPE) or Presentation Controller (PC). It maintains the interrupt context state of each thread and handles the delivery of the external exception to the thread. * XIVE internal tables Each of the sub-engines uses a set of tables to redirect exceptions from event sources to CPU threads. +---+ User or OS| EQ | or+-->|entries| Hypervisor| | .. | Memory | +---+ | ^ | | +--+ | | Hypervisor+--++---+--++---+--+ +--+ Memory | ESB || EAT || ENDT | | NVTT | (skiboot)++-+++-+++-+ +--+ ^ |^ |^ | ^ | || || | | +--+ | || || | | | || || | | +-|--||--||--|-+ +-|-++--+ | | || || | | | | tctx||Thread| IPI or + + v+ v+ v |---| + .. |-> | HW events | | | || | | IVRE| | IVPE |+--+ +--+ +---+ The IVSE have a 2-bits, P for pending and Q for queued, state machine for each source that allows events to be triggered. They are stored in an array, the Event State Buffer (ESB) and controlled by MMIOs. If the event is let through, the IVRE looks up in the Event Assignment Structure (EAS) table for an Event Notification Descriptor (END) configured for the source. Each Event Notification Descriptor defines a notification path to a CPU and an in-memory Event Queue, in which will be pushed an EQ data for the OS to pull. The
